Hoping to resurrect this thread as there's a lot of good information here.
Anyway - I've become interested in building a SDR for WWVB. At this point, as long as I can still get a useful signal, I'm not particularly keen on phase modulation. I'm leaning more toward low, low cost receiver. I recently saw a post somewhere that led me to this GitHub repo for PiccoloSDR where the author has apparently developed code to use the ADC on a Raspberry Pi Pico to implement a direct-sampling receiver.
First question: Opinions on the viability of this as a WWVB receiver??
As long as you are only asking for opinions, and not facts...
I have mind designed a direct conversion WWVB receiver for some time now. I would sample with a 1 bit ADC at 240 kHz. The input signal can be mixed with an LO that consists of the pattern 0, 1, 0, -1 without multiplies. Every other sample can be used as the I and Q signals, giving phase. The amplitude can be approximated by adding the I and Q signals.
For this to work, the sampling rate has to be pretty close to 240 kHz. A VCO can be used by initially syncing it to a reference like a 32,768 kHz crystal (I was trying to keep the design minimal power). 240 kHz crystals exist, but are hard to find. The phase samples should be averaged over 50 ms periods to extract the signal phase. An offset to the VCO can be measured and subtracted out. The VCO should be adjusted to minimize the phase drift. I was going to use a set of binary valued capacitors to trim the VCO. Or, if you can still find them, a varactor would do the job (tuning diode). I think LEDs might make adequate tuning diodes. The DC value on the diode can be adjusted using a 1 bit DAC (sigma delta).
This is not terribly complex, but the devil is in the details. I don't know how hard it will be to keep the 240 kHz oscillator stable. It has to remain stable for ~100 ms, enough so that you can compare adjacent block phase and trim the oscillator frequency to suit.
I almost forgot... the reason a 1 bit ADC will work, is because the oversampling creates a pretty good low pass filter. At 240 kHz, a 50 ms window has 12,000 samples being averaged. I seem to recall the number 6,000 samples in the average, so maybe I was looking at 25 ms windows. It's a trade off between the processing gain (more samples) and timing resolution for signal changes (fewer samples).
I may have mucked up some details. I think I looked at this maybe 20 years ago. lol I was going to do it all in a low power FPGA. SiliconBlue had a family with low double digit static power numbers. Processing at these low rates would not create much dynamic current, so it could have run from a AA battery. Lattice bought SiBlue and when the new 45 nm chip came out, it was more like 100 uA static current.
I should still do this. It would make for a radio controlled clock that could be powered by scavenged energy.