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Line 33: Line 33:
 
<pre>
 
<pre>
  
#define off 0
+
volatile uint16_t clk1000ms=1; // initializing them to 1 insures there is an initial delay cycle
#define on 1
+
volatile uint16_t clk100ms=1;  // when the code first starts, otherwise all timed events would all
 +
volatile uint8_t clk10ms=1;    // happen at once during first run.
  
volatile uint16_t clk1000ms=1; // initializing them to 1 insures there is an initial delay cycle when
 
volatile uint16_t clk100ms=1;  // the code first starts, otherwise they would all happen at
 
volatile uint8_t clk10ms=1;    // once during first run.
 
  
 
ISR (TIMER0_OVF_vect)
 
ISR (TIMER0_OVF_vect)
 
{
 
{
if (clk1000ms!=off)  
+
if (clk1000ms!=0)  
 
{
 
{
 
clk1000ms++;
 
clk1000ms++;
if (clk1000ms>=10001) clk1000ms=off;
+
if (clk1000ms>=10001) clk1000ms=0;
 
}
 
}
if (clk100ms!=off)  
+
if (clk100ms!=0)  
 
{
 
{
 
clk100ms++;
 
clk100ms++;
if (clk100ms>=1001) clk100ms=off;
+
if (clk100ms>=1001) clk500ms=0;
 
}
 
}
if (clk10ms!=off)  
+
if (clk10ms!=0)  
 
{
 
{
 
clk10ms++;
 
clk10ms++;
if (clk10ms>=101) clk10ms=off;
+
if (clk10ms>=101) clk10ms=0;
 
}
 
}
 
// Timer clock is 1mhz, timer is 8bit.
 
// Timer clock is 1mhz, timer is 8bit.
Line 66: Line 64:
 
{
 
{
 
 
if (clk1000ms==off)
+
if (clk1000ms==0)
 
{
 
{
 
// put code here to run every second
 
// put code here to run every second
  
clk1000ms = on;
+
clk1000ms = 1;
 
}
 
}
if (clk100ms==off)
+
if (clk100ms==0)
 
{
 
{
 
// put code here to run 10 times a second
 
// put code here to run 10 times a second
  
clk100ms = on;
+
clk100ms = 1;
 
}
 
}
if (clk10ms==off)
+
if (clk10ms==0)
 
{
 
{
 
// put code here to run 100 times a second
 
// put code here to run 100 times a second
  
clk10ms = on;
+
clk10ms = 1;
 
}
 
}
 
 
 
}
 
}
 
</pre>
 
</pre>

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