VGA question

[Wawavoun]

Hello there !

I am looking for a schematics showing how to get from a Motorola 6845 to a VGA socket and what are the components required to get this working.
I have looking for old graphics card schematics but not found what I need....

I have the Hsync and Vsync on pins 39 and 40 of the 6845 and a signal I can apply to one of the colors on the VGA socket... all in TTL level.

In the actual design of the board this is mixed to get a video signal. I expect to made a direct vga outpout.

I think I have to invert Hsync and Vsync and to reduce TTL to 0.7V peak for color signal. Is that right ?

Thanks for the help. Regards.
Philippe

[Rasz]

well, Baader-Meinhof phenomenon is really strong today. I was just browsing https://hackaday.io/project/167089-isa-8-bit-video-experiments exactly what you want

[Ian.M]

'Classic' VGA modes use a 31.469 kHz line scan rate, which was chosen to be approximately double the US NTSC video format 15.750 kHz line scan rate.  PAL and SECAM video formats have a 15.625 kHz line scan rate.     If its on an existing board, odds are the software or firmware configures the  MC6845 for NTSC or PAL/SECAM timings, which a VGA or SVGA monitor wont be able to lock to unless its actually a wide range multisync monitor that already supports component and composite video using analog era video formats.  If its possible to reprogram the MC6845 for VGA timing,  you'll loose up to half your horizontal resolution (depending on the ratio between the original line rate and 640 px/line VGA line rate).

TLDR: Driving a real VGA or SVGA monitor from a MC6845 in an existing system without a frequency doubling scanline buffer in between usually doesn't work, and if it can be reconfigured to work, looses a lot of resolution so may be unusable anyway. 

[Wawavoun]

Thanks Ian for the explanation...

The board I expect to modify is very similar (at least in the working principles) to the one show in the link indicated above by Rasz.

There is also a ram memory and a characters rom and the 6845 manage the address of both and Hsync and Vsync.

In this design 6845 clock look to be 27.175 Mhz divided by 16. I suppose 16 is the number of pixels of the step of one character to the next.

On my board output shift register clock is 16 Mhz (so this is the pixel frequency) and 6845 clock is 16 MHz / 8 = 2 MHz.

So it should be possible I think...