Having obtained jumper information (thanks Marco), I have been able to reconfigure the MVME211 so it BASICALLY works with my set up. I thought this might be useful for others if I documented my experience here...
First off, I don't have a lot of experience with 68K, so there may well be some school boy errors in here. It's very likely that I've misunderstood something and so treat this information with suspicion and assume that there's at least one serious error (but I don't know where
).
Furthermore, there is a serious problem with testing the board after config. I explain at the bottom of this post.
I'm using revision P of the MVME211. This maybe important because some of my comments refer to component positioning which might have changed.
I'm trying to fit 16 off 32K * 8 RAM devices (HM62256ALP-10). This is going to be configured as two address contiguous banks of 8 off devices, each bank having 256K bytes.
We're going to being using a base address for the whole board of $040000. The first bank will have a base address of $040000 and the second bank will have an address base of $080000
Referring to the PDF attached to one of the previous posts, pg 2.Looking at the jumper pin signal information in the centre of the page, I think it's correct. These jumpers control what signals are fed through to memory device pins whose function varies depending on the device being used. It would be useful to know the function of each jumper group. This is what I found with a continuity tester;
- J1/J3 control what signal is fed to pin 26
- J6/J7 control what signal is fed to pin 1
- J12/J13 control what signal is fed to pin 27
- J2/J4 control what signal is fed to pin 28
- J14/J15 control what signal is fed to pin 23
Given that I am trying to use HM62256ALP-10 devices, there is a massive problem with the above.... If you look at the memory device data sheet, A14 is on pin 1. In the case of a 68000, we need to connect A15 to this pin. As you can see from pg.2 of the PDF, J6/J7 only allow;
to be connected. For this reason, I traced out where to find A15 so I could "hot wire" the correct signal into pin 1. Results as follows;
- A15 is on buss connector P1, row C, pin 23
- This goes to an 'LS373, U22, pin 13
- This signal pops out on U22, pin 12
- This then can be found on jumper pack J8/J16, pin 8
So the upshot is, don't fit any links to J6/J7 but hot wire J8 pin 8 to any pin on the top row of J6 and J7 (the top row pins are linked on the PCB).
In general, Motorola documentation shows the jumpers in the correct orientation (e.g. Rotationally correct when viewing the PCB with connector P1 top-right). There is a major gotcha with J2/J4.
The information is wrong, I think there are two faults and unfortunately there is no easy way of describing this because you can't just rotate or mirror the diagram.
The jumpers are fitted left-right on the PCB, not north-south. Getting this wrong will short the battery and main +5VDC supplies.
In summary, if you look at the PCB;
- The pins nearer the top of the PCB are +5VB
- The pins nearer the bottom of the PCB are for +5VDC
Back on pg.2 of the document, With the above in mind, and assuming you're going to use +5VDC to supply the memory, "most" the example settings at the top of the page are correct but J2/J4 should be rotated 90 degrees anti clockwise and you should also re-number the pins (look at the PCB to see what I mean).
I said "most" because the example of 16K * 8 MCM63128 is actually correctly orientated (but the pins are still incorrectly numbered).
I'm assuming that jumper information for the 2 types of 8K * 8 RAM devices was unintentionally left blank. It doesn't make sense as-is.
Finally on pg.2, I used the "logical equivalent number 4" setting which is for 32K * 8 devices.
Moving on to pg.3 of the document...The RAM devices I'm using have an access time of 100nS (-10 part code) and so I selected "110nS" on J21/J23. This might not be the right thing to do, but it seems to work.
OK. Now the hard part. I found the base address setting really difficult to understand. Here are some comments/thoughts;
All the address selection jumpers are shown rotated through 180 degrees. For example, J9/J17 GND signal is on the RIGHT of the jumper pack when the PCB is viewed in the normal orientation not the left.
The pairs of jumper packs are shown left/right reversed. In other words, the diagrams show J9/J17 to the left of J8/J16. This is incorrect when viewing the PCB in the normal way. Actually J8/J16 are on the left, J9/J17 are on the right.
I can see why the documentation does this, but it's something to bare in mind. (Showing the jumpers this way round makes it easier to read the address bit pattern).
Taking the above into account, it's a shame that the "memory device capacity" table shows the addresss lines MSB to the right (it would work better if it was MSB to the left). Again, not a show stopper, but something to keep in mind when working all this out...
In that same table, there maybe an error at the intersection of "8K * 8" and A15. The table shows X but I think it should be S.
[This is where I make a fool of myself] The biggest problem/error/call-it-what-you-will is the use of bold "BANK 1" and "BANK 2" at the top of each example. This is just totally wrong because (for example) looking at "J9/J17", these are the address selectors for bank 1 and bank 2 respectivly. More generally, jumpers for bank 1 and bank 2 are mixed up across each example. The bold "Bank 1" and "Bank 2" just should not be there.
By way of a further demonstration of my ability to make a fool of myself, here's another one... Just below the bold "Bank" text, there's an area called "Boundary (Bytes)". I think this is "Boundary (Words)". There are two reasons why I say this. Firstly the board is advertised as being able to handle up to 1MB. See the following link (pg. 52);
https://bitsavers.computerhistory.org/pdf/motorola/versados/MVMEVDOS_D2_VMEHwSwConf_May85.pdfand as that table only shows up to 256K bytes a bank, you could only get 512K on the board. Secondly, if we assume that the text "256K" is correct, then we only need A18 to decode each bank if we're talking about words (not bytes).
With all that ranting out of the way, here's how I worked out the base address jumper settings;
Say we want bank 1 to be at address $040000 and we're using 8 off 32K * 8 RAM devices which is 256K as previously stated.
Consider the "Memory Device Capacity" table. Locate the row corrisponding to the device size you're using. So for me, it's "A A A A S S X" which is better read reversed as follows "X S S A A A A". Just to be clear, we're talking about;
A18 A17 A16 A15 A14 A13 A12
X S S A A A A
What this means is that;
- A15 - A12 should be connected to the memory devices (nothing for you to do unless you need to fix a hardware problem as I described above)
- A17 & A16 are decoded on the PCB (nothing for you to do)
- A18 needs setting on the Jumpers
Just to explain in a little more detail; the two S bits of the address enable one-of-four pairs of devices to be selected. These are the four odd and even pairs of devices in each coloum on the PCB.
When I said "A18 needs setting on the jumpers", more accurately I should have said "A18 and above need setting on the jumpers".
Rather than consider all the jumpers in a big bad old mess of jumper-meyhem, just think about J9 & J8. Use the functional desciption and diagram provided top left of pg.3 but ignore their settings and let's start with no jumpers fitted.
Don't fit any jumpers for address bits that contain either an S or A.
For all the high address bits that don't contain an S or A, you need to configure the bit pattern... In our case we have (remembering that I want the base address to be $040000);
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 1 0 0 0 0 0 0
Before moving to the next step, I want to talk about something else... The three example address base configurations provided on pg.3 don't explain how much memory is on the board being configured. I think it's 8K words. The reason for this is that so far we've only been talking about configuring J8 & J9.
We're about to start talking about J10 & J11. It's simple; these two jumper blocks are a bit-flip of J8 & J9 EXCEPT that you don't fit any jumpers for addresses within the block. Reviewing the three example settings, we can see that in all of them, the bit-flip rule works for all the jumpers apart from the bottom two bits. That's why I think the bank is 8K words wide.
Important I don't know if this bit-flip guide is correct; it's just what I observe looking at the supplied information.
So coming back to our example and using the bit pattern above, here's all four jumper settings (1 = fit)
Here's the block base address;
J9 (don't forget that 12 does not count; it's GND)
12 10 08 06 04 02
0 0 0 0 0 0
J8
14 12 10 08 06 04 02
1 0 0 0 0 0 0
Now here's the block base address bit-flipped BUT ONLY FOR BITS OUTSIDE THE RANGE OF THE BLOCK
J11 (Don't forget the 12 does not count: it's GND)
12 10 08 06 04 02
0 1 1 1 1 1
J10
14 12 10 08 06 04 02
0 0 0 0 0 0 0
OK. So that's block 1 sorted. Moving on to block 2, we want a base address of $080000. Here's the settings without the woffle;
J17
12 10 08 06 04 02
0 0 0 0 0 1
J16
14 12 10 08 06 04 02
0 0 0 0 0 0 0
J19
12 10 08 06 04 02
0 1 1 1 1 0
J18
14 12 10 08 06 04 02
1 0 0 0 0 0 0
There's one final step. All the above is "address bit pattern" friendly not "PCB layout" friendly. Here's the same information as above but turned around to make transcribing to the PCB jumpers easier;
J8 J9
0 0 0 0 0 0 1 0 0 0 0 0 0
J10 J11
0 0 0 0 0 0 0 1 1 1 1 1 0
J16 J17
0 0 0 0 0 0 0 1 0 0 0 0 0
J18 J19
0 0 0 0 0 0 1 0 1 1 1 1 0
The MVME110Bug program I'm using has a Block Test (BT) function. Using this shows errors with repeatable faults which is discouraging to say the least.
However if I change the boundaries of the BT function (i.e. Different start and end addresses that still include the "faulty" address from above), the fault goes away.
As an aside, other bug commands don't work, so either there's something wrong with the code or my card; not sure which!
Furthermore, I've written my own memory test program which is fairly simple, but it runs without error for days. I am currently improving this to check that if I assert a single bit in the entire memory block, then only that very bit is high; all the rest are low. Right now, the program only checks that it's possible to write / read 00 and FF to every location using byte or word accesses. Shown below for information, sorry if coding style makes you weep
.
; Simple memory test. Tests 64K byte blocks of RAM.
; Assumes code running on a MVME110 with 110-Bug Version 4.1
; There are four tests herein;
; write-read $00 using byte access
; write-read $FF using byte access
; write-read $0000 using word access
; write-read $FFFF using word access
; You can set the number of 64K byte blocks to test using "blocks"
; You can repeat all the above tests a set number of times using "repeats"
; D Waine 9/05/24
codeStart equ $1000 ; Start of this routine
ramStart equ $40000 ; Base addresss of RAM to test
blocks equ $8 ; Number of 64K blocks to test
repeats equ $2
org codeStart
move.l #$2000,A7 ; Init the stack
; Output welcome string
move.l #testStart,A5
move.l #testEnd,A6
trap #15
dc.w 2
; Set up a counter for number of repeats of all tests to do
move.l #repeats,D1
sub.l #1,D1 ; Make loop count correct for dbra
move.l #0,D0 ; Counts number of times done all tests
bigLoop
; Simple all zeros memory write/read test using byte access
move.l #ramStart,A0
move.l #blocks,D3
sub.l #1,D3 ; Make loop count correct for dbra
block00BLoop
move.l #$ffff,D2
test00BLoop move.b #$00,(A0) ; write 00
move.b (A0)+,D4 ; Read test byte
cmpi.b #$00,D4 ; test for non zero
bne errIn00BTest ; If byte read back in <>0, we have an error
dbra D2,test00BLoop
dbra D3,block00BLoop
; Simple all bits set memory write/read test using byte access
move.l #ramStart,A0
move.l #blocks,D3
sub.l #1,D3 ; Make loop count correct for dbra
blockFFBLoop
move.l #$ffff,D2
testFFBLoop move.b #$ff,(A0) ; write FF
move.b (A0)+,D4 ; Read test byte
cmpi.b #$ff,D4 ; test for non match
bne errInFFBTest ; If byte read back in <>0, we have an error
dbra D2,testFFBLoop
dbra D3,blockFFBLoop
; Simple all zeros memory write/read test using word access
move.l #ramStart,A0
move.l #blocks,D3
sub.l #1,D3 ; Make loop count correct for dbra
block00WLoop
move.l #$7fff,D2 ; Becausee we're working on words, we only need $8000 loops
test00WLoop move.w #$0000,(A0) ; write 00
move.w (A0)+,D4 ; Read test byte
cmpi.w #$0000,D4 ; test for non zero
bne errIn00WTest ; If word read back in <>0, we have an error
dbra D2,test00WLoop
dbra D3,block00WLoop
; Simple all bits set memory write/read test using word access
move.l #ramStart,A0
move.l #blocks,D3
sub.l #1,D3 ; Make loop count correct for dbra
blockFFWLoop
move.l #$7fff,D2 ; Becausee we're working on words, we only need $8000 loops
testFFWLoop move.w #$ffff,(A0) ; write FFFF
move.w (A0)+,D4 ; Read test byte
cmpi.w #$ffff,D4 ; test for non zero
bne errInFFWTest ; If word read back in <>0, we have an error
dbra D2,testFFWLoop
dbra D3,blockFFWLoop
; Bump the test repeats counter and print it out
add.l #1,D0 ; Bump the test counter
move.l #testStart,A5 ; Point at RAM buffer to print D0
bsr bin2Asc32Bits
move.l A5,A6
move.l #testStart,A5
trap #15
dc.w 2
; Go round for another repeat if we need to
dbra D1,bigLoop
; Print bye bye message
move.l #byeStart,A5
move.l #byeEnd,A6
trap #15
dc.w 2
; Return to 110Bug
exitToBug trap #15
dc.w 0
errIn00BTest
move.l #err00BStart,A5
move.l #err00BEnd,A6
trap #15
dc.w 2
bra exitToBug
errInFFBTest
move.l #errFFBStart,A5
move.l #errFFBEnd,A6
trap #15
dc.w 2
bra exitToBug
errIn00WTest
move.l #err00WStart,A5
move.l #err00WEnd,A6
trap #15
dc.w 2
bra exitToBug
errInFFWTest
move.l #errFFWStart,A5
move.l #errFFWEnd,A6
trap #15
dc.w 2
bra exitToBug
errInBitTestNonZero
move.l #errBit1Start,A5
move.l #errBit1End,A6
trap #15
dc.w 2
bra exitToBug
errInBitTestBitPattern
move.l #errBit2Start,A5
move.l #errBit2End,A6
trap #15
dc.w 2
bra exitToBug
err00BStart dc.b "Error in all zero byte access test, exiting to MVME110-BUG"
err00BEnd dc.b 00
dc.b $0d,$0a
errFFBStart dc.b "Error in all bits set byte access test, exiting to MVME110-BUG"
errFFBEnd dc.b 00
dc.b $0d,$0a
err00WStart dc.b "Error in all zero word access test, exiting to MVME110-BUG"
err00WEnd dc.b 00
dc.b $0d,$0a
errFFWStart dc.b "Error in all bits set word access test, exiting to MVME110-BUG"
errFFWEnd dc.b 00
dc.b $0d,$0a
errBit1Start
dc.b "Error in bit test: location <>0, exiting to MVME110-BUG"
errBit1End dc.b 00
dc.b $0d,$0a
errBit2Start
dc.b "Error in bit test: wrong bit pattern, exiting to MVME110-BUG"
errBit2End dc.b 00
dc.b $0d,$0a
testStart dc.b 'MVME211 Test program', $0d, $0a, 'D. Waine 12/05/24 Version 0.1'
testEnd dc.b 00
dc.b $0d,$0a
byeStart dc.b "Exiting to MVME110-BUG"
byeEnd dc.b 00
dc.b $0d,$0a
; Series of routines to convert D0 from binary to ASCII which is stored at (A5). Bump
; A5 before we return. The first routine is the core; all the others just rotate the nibble
; we're currently considering into the correct place
align 2
bin2Asc4Bits
move.w D0,-(A7) ; Save D0
and.l #$0F,D0 ; remove everything above the bottom 4 bits
add.b #$30,D0 ; Turn into ASCII
cmpi.b #$3A,D0 ; Is result greater than "9"?
bmi.s lessThanA
add.b #7,D0 ; hex over 9 look like a letter
lessThanA move.b D0,(A5)+ ; Store result in ASCII buffer
move.w (A7)+,D0 ; Restore D0
rts
bin2Asc8Bits
move.l D0,-(A7) ; Save the whole of D0
ror.l #4,D0 ; Get the high part of the byte into the bottom
bsr bin2Asc4Bits ; And convert it
move.l (A7),D0 ; Recover the number without moving the stack
bsr bin2Asc4Bits
move.l (A7)+,D0
rts
bin2Asc16Bits
move.l D0,-(A7)
ror.l #8,D0 ; Get the hi byte in the lo byte
bsr bin2Asc8Bits ; Convert what was the hi byte of the word
rol.l #8,D0 ; Restore the lo byte to the correct place
bsr bin2Asc8Bits
move.l (A7)+,D0
rts
bin2Asc32Bits
move.l D0,-(A7)
swap D0 ; Get the hi word in the lo part (but save the lo part)
bsr bin2Asc16Bits
swap D0
bsr bin2Asc16Bits
move.l (A7)+,D0
rts
end codeStart
As previously advised, I'm sure that there will be errors/misunderstandings with the above. I'd appreciate any observations/corrections.