Are silicon microbolometers inherently more expensive than conventional CMOS?

[dbooksta]

We're finally starting to see practical thermal imaging sensors (microbolometers) entering the individual consumer market. However, they are still vastly more expensive than comparable visible imaging sensors. 384x288 17µm pixel (i.e., 32mm²) thermal imagers with a fixed manual-focus lens run about $500, whereas $500 will get a 6000x4000 2µm pixel (i.e., 96mm²) CMOS sensor ... plus 5-axis sensor stabilization and a nice zoom lens.

My question: Assuming the same economies of scale were applied as are already used for conventional CMOS sensors, is the manufacturing process for silicon microbolometers inherently more expensive? Or in the limit is it still just some (similar) number of photolithographic steps?

Both sensors can be made from silicon using a CMOS process. The structure of microbolometers looks a little trickier than state-of-the-art visible spectrum CMOS sensors, requiring a thermal bridge for each pixel as well as vacuum encapsulation of the sensor. But I know little of large-scale manufacturing processes, so are these variables significant in the limit (i.e., at scale) on a per-unit basis?

(To elaborate: Thermal cameras look for radiation with wavelengths between 7-14µm, whereas visible light is in the range 0.4-0.7µm. Based on the physics alone, at the diffraction limit microbolometer pixels will have an order of magnitude greater surface area. Apparently commercial sensors are at the diffraction limit for both visible light (at 1 micron pixels) and thermal light (at 17 micron pixels). So, to make it fair, we might compare a 1" 24Mpx visible sensor with a 1" 300kpx thermal sensor.)

[mikeselectricstuff]

There are a number of inherently higher costs - micromachined structures and  vacuum encapsulation for one, but there is also the issue of lower production volumes and lack of competition
 

[dbooksta]

I'm specifically curious about the former: You're saying the uncooled Si microbolometers do require micromachining?  I.e., they can't be constructed through a series of (scalable) photolithographic steps the way other CMOS can?

[T3sl4co1l]

Yes-- you can't very well do a bolometer (which is an array of thermistors, or something like that) on solid, high conductivity silicon crystal.

Tim

[Bill W]

A typical pixel looks like this:



So you have to lay down a material that can be etched away and then deposit the pixel material over the top and finally etch away under the pixel.
A lot of these are on (relatively) small wafers, and I could only guess that the yield is not great, even accepting 0.1% dead pixels.

Underneath and around, before you start the structures is a pretty complex CMOS IC that has analogue parts and quite often a 14 bit 10MHz ADC.

Also as mentioned there is the whole vacuum requirement, either pixel or die, or you have to add on a package cost.

VOx is even less friendly than a-Si for CMOS, which is why FLIR do the lot in house, no CMOS foundry lets anyone deposit VOx !


Bill

[mikeselectricstuff]

https://youtu.be/ny17r03uj9Y

[Kleinstein]

It is not only the sensor that is more expensive. Also lenses for the FIR are more expensive - though in theory they could use mirrors instead.
It is only the image processing and storage that gets cheaper, as way less pixels.

[dbooksta]

Bill: Thanks for that illustration.

So are you saying that etching out the support layer to form the thermal bridge on 17µm pixels is intrinsically failure-prone?  Or are you saying that this fab process is intrinsically not scalable the way the underlying CMOS is (e.g., it will never work on 300mm wafers)?

Also, I haven't been able to determine: Is V-Ox still required for state-of-the-art uncooled bolometers?  They can't be entirely a-Si?

[dbooksta]

https://youtu.be/ny17r03uj9Y

OMG, the poor bolometers!  Are the pixels really that fragile, or is that the result of somebody physically scraping the array?

[T3sl4co1l]

OMG, the poor bolometers!  Are the pixels really that fragile, or is that the result of somebody physically scraping the array?

He blasted the poor thing with some compressed air.  Same effect... atmospheric pressure is pretty beefy against structures so tiny.

Tim

[Bill W]

So are you saying that etching out the support layer to form the thermal bridge on 17µm pixels is intrinsically failure-prone?  Or are you saying that this fab process is intrinsically not scalable the way the underlying CMOS is (e.g., it will never work on 300mm wafers)?

No, just it is a pain to process - which is money.  Most of the manufacturers are just going over to 8" wafer from 6" which is a big capital outlay for the numbers produced.

Also, I haven't been able to determine: Is V-Ox still required for state-of-the-art uncooled bolometers?  They can't be entirely a-Si?

VOx and a-Si are competing materials for the sensing element.  VOx is better for signal to noise/non-uniformity as there's a lot more signal, but it is a bigger pain (=cost) to process.  The higher cost of VOx can be offset by cheaper optics (eg in silicon and lower aperture) or higher sales prices into upper end markets that will pay for performance (eg military).
For most commercial uses, it does not make a huge difference in the end camera as you work with what you've got to get it right.  However given a level optics/processing playing field, a VOx sensor should win every time. 

Generally once a manufacturer is on a course with VOx or ASi they do not change, process development and knowledge is the key in this business.

Bill

[Kleinstein]

The bolometer structures are a little sensitive. One issue with such micro-mechanics is surface tension of liquids. Also breaking the vacuum can be hefty.

In principle this could scale to large wafers too, but due to the extra steps / materials, one can not produce normal CMOS on that line any more. So this will run in special fabs and thus small wafers. At least they don't need fine structures - so no deep sub µm lithography needed.

The structures are more similar to the DLP chips for projectors. These are also quite expensive despite of getting quite some quantity.

[dbooksta]

The structures are more similar to the DLP chips for projectors. These are also quite expensive despite of getting quite some quantity.

Ah ha, that does sound like a good analogy.  So, since I know nothing about the history DLP chips: What kept them expensive even when they went to large-scale production for consumer applications?

[robert_]

The structures are more similar to the DLP chips for projectors. These are also quite expensive despite of getting quite some quantity.

Ah ha, that does sound like a good analogy.  So, since I know nothing about the history DLP chips: What kept them expensive even when they went to large-scale production for consumer applications?

Ultra high aspect ratio (wet, plasma etch etc doesnt work in that direction) etching, especially horizontally, takes very long, reqires specialized (expensive) tools and chemicals and does usually reduce yield quite significantly. Those pixels are incredibly sensitive, immersing the wafers into liquids or any process that involves a flow of some medium over them has to be done extremely carefully and slow (expensive). Just think about how hard it is to get all remaints of liquid etching reagent out under those pixels without breaking them...Surface tension is a huge problem, and you cant just blow it out with pressure or boil it off with heat.
Many procedures that commonly are used on CMOS to do something quick (such as fairly harsh cleaning steps, CMP etc) dont work on that and have to be replaced by more complex, slow alternatives, etc...
Some coatings such as VOx make a terrible mess and contaminate everything, basically making the related equipment useless for any other product.