Another thing to consider about integrating an FPGA, memory and advanced ADCs on a single chip is the looming possibility of a new completely different ADC architecture on the near horizon, which would highly devalue the single chip investment in an FPGA, ADC & Memory.
Something along the lines of the Non-Uniform Sampling type where the "waveform information" is captured in both time and amplitude, and no conventional analog anti-aliasing filter required since the anti-aliasing is "performed" post ADC capture.
SOTA Chip Integration values high quantity usage, where test equipment doesn't qualify. In today's SOTA processes, design cost are astronomical and only justifiable in massive $ markets. Back when LeCroy did their $1M scope they utilized IBMs SiGe BiCMOS 7HP and 8HP process which supported only 180 and 130nm CMOS respectively, and the chip design costs were probably in the few 10s of million $ per chip. Since the CMOS is what the Processors, FPGA & Memory are built in, those features sizes in 7HP and 8HP limit what one can do with CMOS on the these BiCMOS processes, and thus prevented any worthwhile digital implementations on these chips (BTW this is the achilles heal of SiGe BiCMOS!!). Todays design costs in SOTA CMOS are probably 10 to 30 times the investment LeCroy made way back with 7 & 8HP.
So smart test equipment $ likely will focus on just the advanced ADC in whatever process makes sense, and use whatever FPGA & memory required, or roll a custom digital only ASIC which is not an FPGA in whatever processes makes sense. Also don't forget that cramming a bunch of stuff on a single chip increases the chip size, and memory takes up a bunch of space, and chip cost grows exponentially with size.
A complex high performing scope architecture, with FPGA, ADCs, and lots of memory will require an advanced small feature CMOS process to cram everything on a producible size chip, and the design cost and process cost will be unjustifiable considered the limited market.
Best,
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