Where is the Keysight Megazoom V ASIC?

[EEVblog]

If they did develop Megazoom V right after the IV they would probably have to redesign it again as the landscape has changed so much with memory, screen resolution, sample bits, etc.

Yes, I would not rule out that the worked on and/or finished a Megazoom V and then scrapped it.
The other thing that "Megazoom V" would bring them is branding. People know the Megazoom branding, it's one of the if not the most well known branding in the scope business for the last several decades.
Wheter it's ASIC or FGPA or some some hydrib or whatever doesn't matter, they would be crazy not to brand any new technology scope as "Megazoom V Technology".

[EEVblog]

As for 12 bit, that is something that is very, very noticeable. If you do analog, you wouldn't want to go back to 8 bit. Trust me. It is addictive as hell.. That thin line that looks like it came fro best analog Tek that let's you see things you didn't see before...

I can see bit depth being the new must have paradigm shift in the low-ish end scope space.
First it deep memory, you didn't want to buy a scope without it.
Next it was fast update rate, you didn't want to buy a scope without it.
Next it was 4 channels, you didn't want to buy a scope without it.
Cue bit depth...

[2N3055]

If they did develop Megazoom V right after the IV they would probably have to redesign it again as the landscape has changed so much with memory, screen resolution, sample bits, etc.

Yes, I would not rule out that the worked on and/or finished a Megazoom V and then scrapped it.
The other thing that "Megazoom V" would bring them is branding. People know the Megazoom branding, it's one of the if not the most well known branding in the scope business for the last several decades.
Wheter it's ASIC or FGPA or some some hydrib or whatever doesn't matter, they would be crazy not to brand any new technology scope as "Megazoom V Technology".

I absolutely agree!! That is sort of my point. They will call it Megazoom, whatever the implementation. It is the architecture that counts..

[nctnico]

Siglent are on it´s way to convince "people like you"...

Well, the Siglent equipment I bought or recommended in the past decade turned out to be a waste of money sooner or later so no thanks. I'm cured.

Yes we know.
Also you think Keysight scopes are unusable because of your experience with long discontinued 7000 series...
You seem to hold the grudge for a long time.

Wrong on both accounts (and you know it)!

[EEVblog]

If they did develop Megazoom V right after the IV they would probably have to redesign it again as the landscape has changed so much with memory, screen resolution, sample bits, etc.

Yes, I would not rule out that the worked on and/or finished a Megazoom V and then scrapped it.
The other thing that "Megazoom V" would bring them is branding. People know the Megazoom branding, it's one of the if not the most well known branding in the scope business for the last several decades.
Wheter it's ASIC or FGPA or some some hydrib or whatever doesn't matter, they would be crazy not to brand any new technology scope as "Megazoom V Technology".

I absolutely agree!! That is sort of my point. They will call it Megazoom, whatever the implementation. It is the architecture that counts..

I don't think they'll scrap an ASIC, I expect one somewhere though, I just can't see it, too many advantages for a company with the resources and R&D budget of Keysight. Especially in a lower end product where volume matters. And they will be in it for a 10 year timeframe.

[wraper]

If you keep analog front end from 3000T/4000, get rid of aMegazoom IV, put a  single 16GS/s (a variant of?) converter from EXR (which would still get you 4GS/s in full channel mode, instead of 2,5GS/s now) and pipe that into Zynq, you would get immensely more powerful platform than now, and 10bit too.... You would literally solve all of the shortcomings of current platform. Pretty much what Rigol is doing, but with better performing components.

Somehow I didn't notice a better performance overall. Performance of Zinq based scopes fall flat beyond certain performance friendly settings and do not actually reach the performance of Megazoom to begin with. Megazoom based scopes perform well regardless. If Zinq is so perfect, why Rigol rolled out their own custom ASICs for their Ultravision II scopes (with Zinq also included)?

Like I said, "Keysight is fast!" is a U/I responsiveness thing. It is something that "button twiddlers" (people that turn buttons real fast to benchmark how fast scope will respond) notice immediately but rest of people not so much.
It is a credit to how well software in Keysight scopes is written.

I did not write about UI responsiveness at all.

[2N3055]

If you keep analog front end from 3000T/4000, get rid of aMegazoom IV, put a  single 16GS/s (a variant of?) converter from EXR (which would still get you 4GS/s in full channel mode, instead of 2,5GS/s now) and pipe that into Zynq, you would get immensely more powerful platform than now, and 10bit too.... You would literally solve all of the shortcomings of current platform. Pretty much what Rigol is doing, but with better performing components.

Somehow I didn't notice a better performance overall. Performance of Zinq based scopes fall flat beyond certain performance friendly settings and do not actually reach the performance of Megazoom to begin with. Megazoom based scopes perform well regardless. If Zinq is so perfect, why Rigol rolled out their own custom ASICs for their Ultravision II scopes (with Zinq also included)?

Like I said, "Keysight is fast!" is a U/I responsiveness thing. It is something that "button twiddlers" (people that turn buttons real fast to benchmark how fast scope will respond) notice immediately but rest of people not so much.
It is a credit to how well software in Keysight scopes is written.

I did not write about UI responsiveness at all.

OK, fair enough, please explain what do you mean by : "Performance of Zinq based scopes fall flat beyond certain performance friendly settings and do not actually reach the performance of Megazoom to begin with."

Waveforms per second? Is that what you think by it?

[robert.rozee]

[...] Whether it's ASIC or FGPA or some some hydrib or whatever doesn't matter [...]

i'm surprised no one has mentioned risk yet. releasing a product containing a new ASIC carries a high risk, as any design defect within that ASIC can most likely not be fixed in the field. for this reason, there is an incentive to make use of an (old) ASIC that has been well tested in previous products. if you must use a new ASIC design, you at least have to put it through an extreme level of testing to ensure it is 'defect free'. this testing is... expensive.

an FPGA firmware defect, however, is much less severe from the commercial perspective. indeed, if you can identify any defect early on, and quickly produce a customer-installed firmware update, then suddenly your customers will lauder you as hero for backing up your product with ongoing support and development. without necessarily extending the service life of a product, a manufacture may garner customer 'brownie points' by (1) being able to release the product earlier, then (2) providing one or more updates (just bug fixes) that the customer perceives as 'free extras'.


cheers,
rob   :-)

[nctnico]

Risk in an ASIC can be mitigated by creating programmable (statemachine) blocks. I think this is already the case for the existing Megazoom ASICs.

In the end the choice for an ASIC depends on cost reduction per product, engineering costs and the ability to add extra features. AFAIK the ADC is also included in the Megazoom ASICs so there is a significant cost saving for having 1 chip where the competition needs to buy 3 seperate chips (ADC, FPGA and memory) and 'glue' these together.

[Fungus]

Occam's razor says "Cash cow".

Most likely they're still selling as many 'scopes as they can make so they haven't bothered yet.

They probably have a new ASIC in the pipeline ready to go if a serious competitor ever comes along.

There may also be a bit of Fluke factor where managers/purchasers want the same old 'scope they've known for years. They don't want a radical new design or a mixture of old/new devices in the building.

Risk in an ASIC can be mitigated by creating programmable (statemachine) blocks.

They've had plenty of time to test it.

[nctnico]

I still can't shake the feeling that Keysight has hit a dead-end with their ASIC architecture. The DSO landscape has changed to much in the past decade alone. Remember when Keysight introduced frequency analysis on their DSO? Siglent copied it within weeks and 2 years later it is standard on about every DSO model you could buy.

[wraper]

OK, fair enough, please explain what do you mean by : "Performance of Zinq based scopes fall flat beyond certain performance friendly settings and do not actually reach the performance of Megazoom to begin with."

Waveforms per second? Is that what you think by it?

Including that. Once you set something similar to 4 Mpts memory of Megazoom IV, or simply set a very fast timebase (hello GW Instek), capture rate will drop a lot compared to the best case specs.

[nctnico]

OK, fair enough, please explain what do you mean by : "Performance of Zinq based scopes fall flat beyond certain performance friendly settings and do not actually reach the performance of Megazoom to begin with."

Waveforms per second? Is that what you think by it?

Including that. Once you set something similar to 4 Mpts memory of Megazoom IV, or simply set a very fast timebase (hello GW Instek), capture rate will drop a lot compared to the best case specs.

That is only logical; the memory needs to be filled which takes sample_interval * memory_depth of time.

[wraper]

OK, fair enough, please explain what do you mean by : "Performance of Zinq based scopes fall flat beyond certain performance friendly settings and do not actually reach the performance of Megazoom to begin with."

Waveforms per second? Is that what you think by it?

Including that. Once you set something similar to 4 Mpts memory of Megazoom IV, or simply set a very fast timebase (hello GW Instek), capture rate will drop a lot compared to the best case specs.

That is only logical; the memory needs to be filled which takes sample_interval * memory_depth of time.

Obviously, however most of the time is wasted without capturing anything. And Megazoom IV has no such issue.

[mawyatt]

Risk in an ASIC can be mitigated by creating programmable (statemachine) blocks. I think this is already the case for the existing Megazoom ASICs.

In the end the choice for an ASIC depends on cost reduction per product, engineering costs and the ability to add extra features. AFAIK the ADC is also included in the Megazoom ASICs so there is a significant cost saving for having 1 chip where the competition needs to buy 3 seperate chips (ADC, FPGA and memory) and 'glue' these together.

The likelihood of Keysight being able to integrate an FPGA and ADC of calibre for a quality DSO today is questionable. Back in 2000 when we integrated the first RF/MW System on Chip which had an FPGA, Memory, 3 Processors and a full RF/MW Transceiver the FPGA was the most difficult IP to acquire. We successfully did such with a startup in Scotland for the FPGA, but soon after Xilinx acquired the startup and suspended any support. They did so because this startup had some innovative IP and was viewed as a potential threat, so Xilinx acquired them before Altera and squashed the IP. Back then it seemed the high end FPGA market was controlled by Altera and Xilinx, and neither was interested in supporting an FPGA in a custom chip, even for some serious $, we tried unsuccessfully to do so!! Don't think this has changed today since the FPGA IP, which includes the SW, is considered some of the most valuable IP in the semiconductor world, and highly protected.

Which begs the question would Keysight have enough clout, $, influence, market, and so on to pull this off and integrate a high end FPGA, with world class ADCs, and memory and still be profitable, don't think so!!

The advanced research level ADCs Keysight was working with a few years ago, like Stringray (see images), had no such FPGA capability on chip.

Best,

[Fungus]

Protocol decoding aside: How much of a limitation is 4Mb of memory if there's good segmentation and good ability to trigger on glitches?

For large amounts of protocol decoding there's probably better devices anyway. The main advantage of protocol decoding in a 'scope is to match analog events to data transmissions. I'm sure Keysight would prefer to sell you a logic analyzer rather than complicate their oscilloscopes.

[nctnico]

Risk in an ASIC can be mitigated by creating programmable (statemachine) blocks. I think this is already the case for the existing Megazoom ASICs.

In the end the choice for an ASIC depends on cost reduction per product, engineering costs and the ability to add extra features. AFAIK the ADC is also included in the Megazoom ASICs so there is a significant cost saving for having 1 chip where the competition needs to buy 3 seperate chips (ADC, FPGA and memory) and 'glue' these together.

The likelihood of Keysight being able to integrate an FPGA and ADC of calibre for a quality DSO today is questionable. Back in 2000 when we integrated the first RF/MW System on Chip which had an FPGA, Memory, 3 Processors and a full RF/MW Transceiver the FPGA was the most difficult

By programmable I don't mean FPGA but having statemachines that can be programmed using microcode. More in terms of having function specific softcores inside the ASIC. It makes more sense to have a programmable statemachine to implement complex triggering for example compared to creating it in logic anyway. The same goes for math and protocol decoding; a programmable statemachine is likely more effective in terms of amount of logic (chip area) and ASIC validation / testing time. Although care must be taken not to postpone the design & implementations of the algorithms that need to run on the statemachines to the software development phase. Validation of the algorithms must be part of the ASIC development process in order to prevent nasty surprises.

[mawyatt]

Another thing to consider about integrating an FPGA, memory and advanced ADCs on a single chip is the looming possibility of a new completely different ADC architecture on the near horizon, which would highly devalue the single chip investment in an FPGA, ADC & Memory.

Something along the lines of the Non-Uniform Sampling type where the "waveform information" is captured in both time and amplitude, and no conventional analog anti-aliasing filter required since the anti-aliasing is "performed" post ADC capture.

SOTA Chip Integration values high quantity usage, where test equipment doesn't qualify. In today's SOTA processes, design cost are astronomical and only justifiable in massive $ markets. Back when LeCroy did their $1M scope they utilized IBMs SiGe BiCMOS 7HP and 8HP process which supported only 180 and 130nm CMOS respectively, and the chip design costs were probably in the few 10s of million $ per chip. Since the CMOS is what the Processors, FPGA & Memory are built in, those features sizes in 7HP and 8HP limit what one can do with CMOS on the these BiCMOS processes, and thus prevented any worthwhile digital implementations on these chips (BTW this is the achilles heal of SiGe BiCMOS!!). Todays design costs in SOTA CMOS are probably 10 to 30 times the investment LeCroy made way back with 7 & 8HP.

So smart test equipment $ likely will focus on just the advanced ADC in whatever process makes sense, and use whatever FPGA & memory required, or roll a custom digital only ASIC which is not an FPGA in whatever processes makes sense. Also don't forget that cramming a bunch of stuff on a single chip increases the chip size, and memory takes up a bunch of space, and chip cost grows exponentially with size.

A complex high performing scope architecture, with FPGA, ADCs, and lots of memory will require an advanced small feature CMOS process to cram everything on a producible size chip, and the design cost and process cost will be unjustifiable considered the limited market.

Best,

[2N3055]

Protocol decoding aside: How much of a limitation is 4Mb of memory if there's good segmentation and good ability to trigger on glitches?

For large amounts of protocol decoding there's probably better devices anyway. The main advantage of protocol decoding in a 'scope is to match analog events to data transmissions. I'm sure Keysight would prefer to sell you a logic analyzer rather than complicate their oscilloscopes.

Limitation is that there is NO 4 Mpts of memory. It is 4 divided by 2 for ping-pong buffers, then by 2 for shared channels, and then again by 2 if you use MSO digital channels. So it goes from 2Mpts for single channel best case scenario to 512kpt worst  case...
With segments, even worse.

Example:
MSOX3104T: One channel active. CAN bus decoding. 50us/div, to fit one packet across the screen. Segments set for 64 segments (packets in this case). Sample rate : 12,5 MSa/s.

SDS6104H12: One channel active. CAN bus decoding. 50us/div, to fit one packet across the screen. Segments set for 64 segments (packets in this case). Sample rate : 5 GSa/s.

If you're only decoding, it doesn't matter. If you're looking to see high frequency interference in signal, that confuses devices on  a bus, it matters a lot.

It is not even LARGE amounts of decoding or large time bases... 100us per division already makes it sample at 625MSa/s .
At 200us/div you are already at 250MSa/s that puts you in Rigol 1000Z and Micsig territory.  At 1ms/div you are at 50MSa/s. And that is SINGLE channel per ADC. You enable channel pair, and it all halves. And all the time you are having full 1GHz front end bandwidth piped into it.

As for good triggering on the glitches, even SDS2000X+ has full set of triggers and zone triggers equivalent to 3000T. Rigol 5000/7000 and up also have it all.

Siglents have better analog noise performance, Rigols have 4 math channels, and 4 decode channels.

[rf-loop]

Afaik, what ever this matters or not but is it so that MZ IV do not have digital trigger engine. Do it have conventional old side pathway analog trigger system.
And I did not say or made guestion is it good or bad. Only what is fact.

[jc101]

I think Dave needs to have a real thorough search in the dumpster room, the Megazoom V could have slipped down behind a bin or something...

[Someone]

I think Dave needs to have a real thorough search in the dumpster room, the Megazoom V could have slipped down behind a bin or something...

That does feel like where this is headed....

[EEVblog]

Occam's razor says "Cash cow".
Most likely they're still selling as many 'scopes as they can make so they haven't bothered yet.
They probably have a new ASIC in the pipeline ready to go if a serious competitor ever comes along.

IIRC the previous average time between releases of Megazoom ASIC was 6 years. So based on that they should have been developing the Megazoom 5 from at least say 8 years ago (3 years after release max). They probably didn't know the IV would last them 11 years, it would be impossible to predict that.
No doubt the IV has been a cash cow for them, but at what point did they realise that, and that they could just cruise with it for now doing on 11 years?
Was a follow up product developed and they didn't release it because they ran the numbers and decided to just milk the cash cow instead?
I can't believe there is no follow-up product architecture ready or almost ready for release. And a substanital new product release can't just milk the Megazoom IV cash cow again (they have already done that several times), so it needs a new architechure, and as mentioned, it has to be the Megazoom V for marketing reasons.

[EEVblog]

Another thing to consider about integrating an FPGA, memory and advanced ADCs on a single chip is the looming possibility of a new completely different ADC architecture on the near horizon, which would highly devalue the single chip investment in an FPGA, ADC & Memory.

You can now get 64GS/s ADC's on FPGA's 
https://www.intel.com/content/www/us/en/architecture-and-technology/programmable/analog-rf-fpga.html

[nctnico]

Another thing to consider about integrating an FPGA, memory and advanced ADCs on a single chip is the looming possibility of a new completely different ADC architecture on the near horizon, which would highly devalue the single chip investment in an FPGA, ADC & Memory.

You can now get 64GS/s ADC's on FPGA's 
https://www.intel.com/content/www/us/en/architecture-and-technology/programmable/analog-rf-fpga.html

IIRC You can buy a couple of cars for the price of one of those FPGAs. An ASIC becomes cost effective quickly especially if you have developed ASICs before.