Maybe you will find these helpful.
Yes, thank you. Much interesting on your YouTube channel!
I noticed you were using the Standard Deviation value for measuring the jitter. My datasheet (TUSB1310A TI USB 3.0 PHY) above states that if an external oscillator is used, its "absolute p-p" clock jitter should be less than 50 psec. This seems impossible since the p-p jitter is unbounded and the actual built-in oscillator measures around 300 ps p-p. Likely they mean "std dev"? And what is this business with "reference clock TJ with JTF (Jitter Transfer Function) total p-p" of 25ps? The note says calculated as 14.1 x RJ x DJ. That would require (RJ + TJ) to be < (25ps / 14.1) or less than 1.77ps
All this is like walking in a hall of mirrors...
I'm still reading in on the subject and I will look into the EZ-Jitter Plus software installed on my Agilent scope. But I really would like to understand this analytically.
On a brighter note: I figured out why my oscillator was some 1.5KHz too high. The external load capacitance was incorrectly calculated. When increasing to 33pF, which meets the crystal's total load capacitance of 18pF, the frequency is spot on (within 1PPM). However, it drifts some 200 Hz down when the board heats up from 25 degC to around 50 degC. This is expected since the XTAL used only has a +/- 50PPM temperature stability. I have ordered one with +/- 10 PPM on both frequency and stability over temp spec. Hopefully this will reduce the temp drift.
On a negative note: My PHY still doesn't lock. Next test would be to rework the board to disable the SSC to see if it makes a difference.