Well the intermittent display fault has returned to my HP 54615B, trouble is after the second power up, the Hsync/Cal signals don't stay borked for long enough, to see if they are failing at the same time as the display, the signals are correct before the CRT fully warms up and the picture appears.
Hsync & cal signals measured, before they quickly corrected themselves to 19.72kHz (Hsync) & 1.2kHz (probe cal).
I can't find the "any" key.
David
Is there warmer than usual?
Our freezer has removable shelves.
Pretty optimal for cooling bigger things.
80Mhz clock and 1/4 slower sync.
How is this clock generated?
A far fetched.
Sort of direct lines out of the machine, says xDevs 54600A schematics.
Pages 22-23/125 there have +5VF_Core, its buddy +5VF_Pad is clipped but component numbers are still present.
Can you show your version of them some cold spray?
I guess it was a little bit warmer when I acquired it (Jan 2021), it hasn't been used much due to this fault, when last used in December, it required about an hour warm up time, before the horizontal display would lock.
Temperature was around 18°C to 23° (depending which crap thermometer I look at) in the workshop when I checked over the weekend. I've no freeze spray ATM and our freezer sleeves are the plumbing, i.e non removable unless you want to destroy it.
Both the HP 54600A & 54654N use a custom IC (Foxy for 54600A & Jackal for 54654N) to provide the H & V Sync signals and the probe cal signal is divided down from the H-Sync by a 74393, the custom IC has a 40MHz clock input, could check this in the future.
I have to thank whoever posted the 54654N CLIP, as the part # of the Jackal IC is the same one used in my 54615B, around it is the 40MHz oscillator & 74393 IC.
David
Dang, I meant fridge, our freezer has drawers and compressor is eating some bottom area.
But freezer would be better, then you can store its stuff into the fridge and "save" energy.
And dang, oscillator idea out of the window.
Single 40MHz crystal is not very easily going to output 30MHz.
54600A schematics has that same thing but I missed it.
The picture seems to be pretty same, Foxy clock line continues to 74F32 OR gate, is it there also?
The edge part is clipped again but seems that the gate is between the crystal and a clock pin.
A last straw maybe.
Or maybe not, unexpected wait state can also do something like that but from where I have no idea.
I have only that 54600A schematics from xDevs, can't find anything else, different names yes but contents no.
(here search of 546 clip had one result, now two)
There I saw a 10MHz crystal with differential drivers of around 1GHz speed and finally outputting 80MHz to Aspen.
That decoration can more easily output only 3/4 freq. but being a source for H-sync of other chip with its own clock is a bit far, if not that unexpected wait state.
Foxy chip seems to be more in control with timings but maybe Jackal still has an easy access to other clock output to check how its freq. is doing when H-sync is wrong.
If you can see that slow sync picture can you figure out if some other parts are also slow?
Like some calculations or widths being wrong.
Maybe your 18-23 temps were just some air flow and indicating that somewhere is a cooler spot.
Big mass spray cooling can be disturbing, you never really know how it really is.
Cool concrete floor and over night storage on it may also be enough.
Then obviously testing without moving it.
And afterwards learning that your delicate test setup was partially disconnected, not much, just a ground here or there.
Old PC CGA lowres H-sync was 15.7kHz, maybe that kind of a monitor accepts a bit too slow stuff.
I also remember a VHS copy protection system where sync was intentionally out of sync.
Since recording needed precise timing it didn't like that out of sync stuff but TV wasn't picky, and had no problems.
So old video monitor can also be almost ready made picture maker but finding its separated sync signals can be less easy.
And then it probably fails when H-sync is correcting its act.
Maybe, finally, easiest is to do a general purpose MCU controlled double frame buffer thingy that can read anything it can see and transform it to what ever is needed.
CGA to VGA converters are generally accepting 14.5kHz H-sync but auto scan sync polarities are hazy and none seem to accept old MDA or HGC frequencies.
See the Agilent 54645N CLIP on archive.org, posted by BD139 a few weeks back, when Vince bought his HP MSO, be warned it is a mass of jumbled up pages.
Actually you're pretty good with the 54645 scope on service information. There are two documents of interest:
Firstly the user and service manual (module level) is here:
https://xdevs.com/doc/HP_Agilent_Keysight/HP%2054645A,%2054645D%20User%20&%20Service.pdf
Now here's the good one, the CLIP (component level information package) is here. All 300Mb of it
https://archive.org/details/HP54645NCLIPImgs
As mentioned in the thread I bounced the parts for reasonable money on their own. Yours is profitable on that front even if it's knackered. In the end I sold the good plastics, the knobs, motherboard (£25 even though it was broken), display assemly and power supply separately and made 2.5x what I paid for it
If it works the only maintenance risk is the Dallas RAM module and the RIFAs in the power supply board really. They are top notch bits of engineering.
David
The rest of the Jackal section from the CLIP images attached below, 40MHz clock is the standalone oscillator module, Dot-CLK seems to be an output going to the COMBO-PAL (prog array logic) IC shown in the thumbnails above.
And yes if I adjusted the appropriate hold control on the CRT board, I could get it to slow the horizontal roll enough to see the picture, but it was very unstable and would quickly drift back to a fast roll. Picture taken in January last year.
David
Bent picture is very good, exactly what is expected.
Foxy, after those clocks, seems to be mainly a memory controller.
So not very much to do with other timings.
Foxy Dot_clock goes to 74LS194 and is clocking out brightness values.
Bent grid is shaped exactly how wrong speed of line should be, all dots are equally slowed with the H-sync.
Since H-sync is just a pulse it defines only a starting point, monitor does the rest.
Monitor is deflecting just like it is and despite the data, it's data who's job is to be in sync.
If Dot_clock is what it is intended to be then dots are also positioned accordingly, so grid's dot square would still be square.
So Dot_clock is equally slowed and reason seems to be overall clocking of the chip.
COMBO_PAL has also that LvRAS as CLK1, together they can do that 3:4 timing but HS is elsewhere.
Dot_clock is also looping pixels through U97 linebuffer for PAL display.
Separated H-sync error is not very probable.
How pure crystal that 40MHz clock is?
Foxy clock has that OR gate but no clock chip enable pin and Jackal is the opposite.
Clock chip's manual say it can be as slow as 26MHz, how is it done.