Well, the discrete ADC design has got from this simulation:
to this, running on actual hardware:
Proof that all this test gear does actually get used, even if it is to design more test gear!
It's fudged at the moment - a corner of the FPGA is pretending to be the analogue electronics to the rest of the FPGA - but at least it's wiggling the right wires in the right way and responding to feedback from the faked current steering, integrator and comparator. Looks like the next step is a dive into PCB design and see if I can get a board before the usual
"Can't get anything done because it's Christmas". I love Christmas, but it's a right pain in the arse that what can normally happen by
"next week" suddenly becomes "
2nd week of January" as soon as Christmas looms.
Added to the whole "
nearly Christmas" thing the PCB design which would normally be a one to two day job will stretch to three or four because for
this baby I'm going to want to add in a lot of carefully thought out test points, built-in Z
0 probes and logic analyser takeoff points becuase I know that if I don't this board will be hell to debug, and if I do add all that it'll probably all work first time rendering all that work pointless. Sheesh, the price we pay for Murphy!
It doesn't trigger reliably at the moment, which suggests that I've got a timing issues that doesn't show up in simulation (where it works perfectly every time) but only on real hardware. Still, it's on an FPGA so I can safely move to "solder state" and debug the timing issue once I'm on a PCB with some minimum guarantees about signal integrity rather than the tangle of wires it is at the moment. Vis: