Finally, I found the source of much grief: The reference buffer that supplys the two (hopefully identical) signals to the measuring device. Somehow I decided it would be a good idea to go with "combine 2 inverters per output channel", whilst beeing all tied together on the inputs. As it turns out, that induced a lot of random jitter between the channels. Enough to make looking at noise performance of my actual device under test a boondoggle. The new topology splices all inverters together through individual series resistors and the outputs are hooked up like a resistive splitter. This way, the signal has a nice impedance and to be very similar on both channels (given both are terminated into 50
). At least thats what I hope.
To not make more of a fool of myself I continued to actually measure the new distribution, sadly no pictures from before.
As can be seen they are close. The -86ps should be delay from the length difference in the sma cables used for hookup.
TIL: Logic gates can introduce random jitter. A lot more than I thought
Although I am not sure, but cycle-to-cycle jitter still looks not so good for a precision 10MHz source? Any opinion on that?
To be specific I fear my "unbuffered inverter as wideband limiting amplifier" implementation might have bad performance in that regard?
Edit: Oh FFS one of the outputs has fallen off