I think you’re insane ![Laughing :-DD](https://www.eevblog.com/forum/Smileys/default/smiley_laughing.gif)
Realistically these shouldn’t be terrible to place but you’d need a stencil, solder paste, hot air to do it properly. The killer of course is the possibility of bridging pads. Undoing that mistake is risky as braid can lift the solder mask. At which point you’re up shit creek.
Good luck.
The former is taken as given, both the questionability of my sanity and the necessary tools and techniques.
I'm gravitating to stencils as the norm, now I know I can successfully cut my own on the plotter I've even been using them for those little purchased SMD adapter boards.
The thing that's driving this is that increasingly I'm encountering parts that are
only available in itty bitty leadless packages. So far that's not been a showstopper, but someday soon I'm going to find a part that I really want/need that's only available in 'stupidly small'. I know that in the past I've passed over ICs because of that. So, I can either keep going "
Too small!" or learn to cope with them (or not, whichever ultimately proves to be the case).
Avoiding rework is an issue, hence the desire to get some practice in, both in applying the little sods and learning what makes a good and what makes a bad footprint for them. Tasks for today are (1) do the supermarket shop, (2) read through a Texas Instruments paper on QFN footprint design (scba017d), (3) finish design of a footprint for that package, (4) do an adapter board design that includes it.
On the last point, the adapter board design: I'm down to my last 3 SOIC-16 adapter boards. I had a suspicion, and after checking it out it proved to be right - namely that I can get JLCPCB to make me a few panelised adapter boards cheaper than I can buy ready made ones. I thought I might as well design some with optional decoupling caps on and get them made up. While I was at it, the effort of including a 3.5x2.5mm QFN footprint for experiment/practice seemed worth expending.