Building my own scope

[Mechatrommer]

Of course they do. Why else would their sampling capability be listed in every datasheet in GSa/s ?

Read David his post.

The way I read it, is that according to him sampling is charging a capacitor with an analog value, not the turning it into a digital value. It is semantics.

I did also Mech's, rob77's and tggzzz's earlier all with some amusement.

But you just can't get away from facts, a DSO samples.....fast !

to be pedantic, my tongue can sample every food in restaurant and later pick which one i like, so i have a "sampling" tongue. a doctor will sample blood from various people to know where covid originated, so we have sampling doctor etc etc... albeit links are provided earlier from Tektronix and Keysight, some people still failed to read they generalized the term "sampling oscilloscope" as either 2 classes of equivalent or random sampling (or mix) where BW>>sampling rate.. and the other larger class is what we know "digital storage scope" (heck who are so pedantic to type all those?) or DSO as general purpose scope where sampling rate > 2 x BW. even analog scope will sample something into the CRT, so will it make it a "sampling scope"? its semantic of the same thing but different term or vice versa, some want to narrow them into classes and some still want to generalized for all classes as one. so looking at the topic... lets be more pedantic...

[pcprogrammer]

Virtualy any ADC does. Continuous-time sigma-delta ADCs are the only exception i'm aware of.

A sigma delta converter is in itself a kind of sample and hold device. It keeps track of the input signal and checks if it goes up or down on the next clock.

A flash ADC might not need a sample and hold because it uses many comparetors to make up the output bits, so clocking just the outputs might do well.

[tggzzz]

And what he, and me too, wonders about how this works for a high speed ADC. Does it use a sample and hold circuit or not.

There are many many types of ADC.

One type is a flash converter. An 8 bit flash converter contains 256 analogue comparators, each of which compares the input voltage with one voltage somewhere "along2 a 256 resistor potential divider. The output of the 256 "one-bit ADCs" is converted to an 8-bit number by combinatorial logic. That combinatorial output will continue to change while the input is changing. A separate 8-bit latch is then used to capture the output at a suitable instant, the sampling instant.

A variant of that is to have 256 latches, one for each of the 265 1-bit ADCs. Subsequent processing reduces the 256 digtial signals to an 8-bit number.

EDIT: I see our replies crossed in the æther!

[tggzzz]

Virtualy any ADC does. Continuous-time sigma-delta ADCs are the only exception i'm aware of.

A sigma delta converter is in itself a kind of sample and hold device. It keeps track of the input signal and checks if it goes up or down on the next clock.

It can be analysed as a dithered 1-bit ADC with subsequent digital signal processing.

[tautech]

Do you think the sampling dots in a DSO in Dot mode are just invented ?

Actually the original FNIRSI-1013D does invent (calculates) them when the input is above 44MHz 

They haven't got that to themselves. Back in 2010 a member reported the early Rigol's doing similar things.

[gf]

A flash ADC might not need a sample and hold because it uses many comparetors to make up the output bits, so clocking just the outputs might do well.

Ideally yes, but In practice a proper sample-and-hold usually enhances the dynamic performance because of the inevitable timing mismatches between comparators (-> close the S&H aperture, let the comparators and priority encoder settle, and then latch the digital output).

[David Hess]

So the distinction basically is that sampling means charging a capacitor to the analog voltage at the input and not the conversion to digital to make a digital sample.

It does not have to be a capacitor.  Fast samplers can use a transmission line in place of a capacitor, and a traveling wave gate sampler has no extra storage element.  There are some old designs which use an inductor as the storage element but I do not think these were ever used for digitizers.

Hence the assumption that a DSO uses sampling.

Very confusing unless you know the history of the technology. 

I think of it as three difference classes of oscilloscope:

1. Some very old DSOs (digital storage oscilloscopes) used non-sampling ADCs.  This has performance disadvantages but can work at lower bandwidth.  High speed track-and-holds and samplers are not trivial to design or implement, and for a long time they remained separate from ADCs.

2. DSOs (digital storage oscilloscopes) generally use sampling ADCs of one variety or another.  In the past the sampler was a separate stage preceding a non-sampling ADC.  The frequency response of the sampler has the standard single pole -6dB per octave roll-off based on its time constant.  Most or all of these are really using a track-and-hold and not a sampler, which adds to the confusion.

3. Analog and digital sampling oscilloscopes place the sampler at the first stage of the input signal chain and use a sampling strobe width much shorter than the time constant of the sampler.  This produces a non-linear frequency response based only on the sampling strobe width as shown below.  RF sampling voltmeters also work this way.

And now the question is how this is done in very high speed ADC's because the charging of such a capacitor for taking the sample is possibly to slow to do this. For this I don't know the answer.

I do not know how they do this, especially since these are pipelined subranging ADCs which use charge redistribution.  Maybe the sampling capacitance really is that small?

I entirely agree that - to put it overly simply - one type of sampling captures the average voltage during a period, and another captures the average voltage at an instant in a period. The two types' very different aperture times lead to differing characteristics, advantages and disadvantages.

When the sampling gate width is much smaller than the time constant, like in a sampling oscilloscope, then the average voltage is captured.  The sampler in a digital storage oscilloscope does *not* capture the average and operates as a track-and-hold with the bandwidth determined by its time constant.

Nonetheless they do both provide representations of the input voltage at discrete time intervals - and that is the key distinguishing feature of sampling vs analogue processing.

It is a distinguishing feature between sampled data systems and continuous time systems.  Sampling works just fine with analog processing and analog sampling oscilloscopes exist.  The discussion here is about two different types of sampling which produce very different results and the two different types of oscilloscopes which make use of them.

A flash ADC might not need a sample and hold because it uses many comparetors to make up the output bits, so clocking just the outputs might do well.

Ideally yes, but In practice a proper sample-and-hold usually enhances the dynamic performance because of the inevitable timing mismatches between comparators (-> close the S&H aperture, let the comparators and priority encoder settle, and then latch the digital output).

Some flash converters were better than others at handling dynamic inputs, and adding a sampler could improve the bandwidth tremendously of any ADC.

The Tektronix 468 used the TRW TDC1007 20 MS/s flash converter which was advertised to *not* require a sample and hold amplifier up to 7 MHz, at least according to the datasheet.  The Tektronix specifications say 10 MHz of useful storage bandwidth, but that seems to be based on the Nyquist criteria.  The 468 implements jitter correction but not equivalent time sampling.

The Tektronix 2230 which followed the 468 used a Sony CX20052A 20 MS/s sub-ranging converter which *must* be used with external sampling in a dynamic application.  Sony had a companion track-and-hold but Tektronix implemented their own higher bandwidth discrete solution.  The Sony datasheet does not say what the input bandwidth of their ADC was, which might be considered a comment saying that it was abysmal.

[pcprogrammer]

The talk about ADC's made me look at the datasheets again, of some that are used in scopes I have here and now I get why they show a delay in time on samples taken and output on the digital bus.

They use pipe lined architectures to make the high speed and in the mean time reduce on power used. The AD9288 shows a track and hold part on the input, so it does sample the input before doing a conversion. This one is not that high a speed. 100MSa/s at max.

The ADC08D500 is much faster and mentions a pipeline delay of 13 clocks. The block diagram shows a sample and hold part on the input, which is more or less the same as the track and hold.

Interesting stuff