Tektronix TDS744 CRT to LCD color converter FPGA module DIY

[spo256al2]

Hello,
This topic describes LCD color converter FPGA module experience for broken CRT on TDS544 TDS724 TDS744 TDS754 TDS784
 I bought on ebay a TDS744A tektronix oscilloscope as a part. As often this scope as a weak brightness CRT and it is very difficult to find a new CRT. On the net some users have changed the CRT by LCD. They use analog scope VGA output to send signals to a Chinese board which converts analog signals in digital signals to LCD display… Perhaps a more direct solution can be used by taking digital signals directly from the RAMDAC scope. I saw that a company did it. But I thought it was the right time to have my first experience with the FPGA by building my own solution.

It is easy to find service manual and schematic on the web , thanks to kO4BB download - KO4BB. As TDS7XX family as very near hardware as TDS520B, I used the TDS520B schematic for my TDS744 experience.

There are 60 frames per second. Each frame contains (visible) 480 lines of 640 pixels.  A pixel is build by  mixe 3 primary colors: Red, green, and blue. By modifying the intensity of these primary colors, you obtain one the pixel of the color you want. As an artist on his wood palette with watercolor. 
To build the frame, the scope uses a video RAMDAC chip: BT471 or ADV471. The datasheet gives most of the information you need and the TDS 520 schematic gives the rest.

The BT471 use color palette and overlay palette loaded in dedicated RAM and digital to analog converter to output VGA signal.
To display a frame, the scope separates the picture into two types of elements one is curves ( Named overlay palette in BT471 )and all of the other stuff as grid, index, buttons… (named color palette in BT471). The scope displays either the curves or the other stuff.


In the BT471 each color palette or overlay palette uses  3 registers of six bit length: one register for Red, one register for Green, one register for Blue. There are 256 colors palette in the BT471, so 256 registers form a RAM bloc for each primary color and 15 RAM bloc for overlay palette. There is a pixel mask register in BT471 but it is not used in the scope. The scope set all Pixel bit mask register to ‘1’.

So, to display a pixel, the scope sends to the BT471 the address of the color or overlay and the BT471 DAC convert in analog to display the pixel.
At startup, the oscilloscope fills the entire palette with colors and overlays. All this is sent to the BT471's data bus. There is only one pixel mask fill sequence, followed by the address of each pixel with a value for each of the three primary colors, red, green, and blue. BT471 internal logic handles this sequence to load RAM

The scope hardware limits the color palette to 16 colors and 15 colors for the overlay. 
To use an LCD display we roughly need to get the color data from each RAM output, before the DAC. As this possibility is not given by the BT471 RAMDAC, the idea is to sniff the pins RAMDAC and emulate the RAMDAC by a FPGA and send the pixels to the LCD.
To emulate the RAMDAC by a FPGA I reproduce the internal functions of the BT471 : Pixel mask, color address, red, green, blue color registers, RAM blocs, and internal logics. The internal logics was done in Finite State Machine
The FSM is use at the start up to write primary colors into each RAM bloc.
 Function_diagram.pdf (329.56 kB - downloaded 134 times.)
For the FPGA I used an Xilinx Spartan XC3S200 development module (bought in suplus) and I built a PCB to plug the dev board on the BT471.
As the first design PCB was several times modified, it is very dirty and there is colors error intermittently. So, I am drawing a new PCB design.

Here a link for the youtube video https://youtu.be/v6Kjz3UYjVk



At the video starting you can see the yellow LED for the loading RAM from the finite state machine.
I learned VHDL to build this project and I'm sure I didn't respect the state of the art. Bear with me.

Vincent

[nctnico]

That is neat. I like the way to use the QFP socket to connect a chip to an existing board. I never thought of that. I did something similar in the past but using a fixed palette by taking the 5 bit color data that goes into the RAMDAC.

[spo256al2]

Hello,

To nctnico. Yes !!! I built your design and I studied your code and I did a PCB. It ran Thanks.

At the moment I am working on a new PCB with my solution.
Below it is my VHDL source code according to the hand drawing diagram on the last post

RAM_DAC.vhdl is the "main"
FSM.vhdl
MUX_4.vhdl
PIX_MASK.vhdl
RAM_VIDEO.vhdl
REG_8.vhdl
RAM_DAC.ucf is the constraint file for XMF3_g_200 FPGA module with XC3S200 xilinx from PLDkit low cost module compagny.
I know that module is obsolete but with the code source you can use it, on a spartan 7 or other FPGA

The display used is  a 640x480  G065VN01_V1 I bought it on ebay and the inverter to Aliexpress

Vincent

[TERRA Operative]

Ooh, I am interested in this!
I have no programming experience, so I can't help with that bit, but I am interested in replicating it myself once it's working.

Is the LCD you used a good fit, and does the image line up with the side and bottom buttons around the display?

[spo256al2]

Hello Terra,

I just receive the PCB board you did for testing my intermitenly faulty TDS PSU  !!



Yes, the LCD fit all right, I chose its size to fit direcly in place of CRT.
I plan to power the LCD and FPGA PCB module with the 21 volts from the microprocessor board. This 21Volts is used to power the CRT assembly

Vincent

[TERRA Operative]

Nice! I hope it helps you get your PSU working.

[spo256al2]

Hello,

I did the new schematic and PCB drawing for the CRT to LCD converter module. I will order it JLCPB.
I seen that xilinx FPGA is difficult to get on Mouser or Digikey but available at Aliexpress. Palette_LCD_V2_schematic.pdf (96.29 kB - downloaded 128 times.)

Vincent

[Tantratron]

Hello Vincent,

Great initiative where there will more and more need of such LCD-TFT kit, these TDSxxx/A/B/C/D are really incredible Oscope.

You mention a company or person in USA who did such kit (Simmconn Labs - Mr Xu Wang). I did purchase one unit from him and later two of my customers in Europe purchased a total of 1+3 units (two of these units were in my hands to repair the repspective TDS oscilloscope). The product is well designed, astute but expensive plus the LCD-TFT is not of good quality regarding angle of view, brightness.

I understand after discussing with the owner in USA that he was using initially an old TFT-LCD with very good contrast (HITACHI model TX17D02VM2CAA). Later HITACHI stop producing the unit so later Xu decided to use another LCD-TFT ( AUO model G065VN01 V2) but the display contrast, brightness, quality really dropped.

In fact on his eBay publicity, he shows the HITACHI setup but sells AUO setup which can be misleading in my opinion. Technical discussion attempt with Xu was not easy neither productive so my recommendation would be to go after a better LCD-TFT display. The problem is the old form factor 3x4 and the voltage translation required (5V versus 3.3V) but you seem to have done the hardest part, namely the FPGA programing then insertion top of U199 chip.

Anyway glad to see a french (european) initiative, encore bravo pour votre travail.

Albert

[ltarjanyi75]

Hi spo256al2!

"Can you help me how are you driving the LCD display? As I see in its documentation, it has differential inputs. Have you created differential ports on the FPGA or do you have some other circuit between the display and the fpga?"

Update:
I see that I was looking for the document of V2 display, which has different input than V1 which has TTL/RGB inputs.
I guess that the fpga code could be modified to fit this version also. Will try to do that...

Thanks!

[spo256al2]

Hello itarjanyi75,
This adaptator was design for V1 display. As I provide the code, you can modification the code as you want. But I know that a logic chip can change parallel TTL to serial LVDS. On aliexpress you can find this kind of adaptator.
Regards

V.

[ltarjanyi75]

Hi Vincent!

Do you have any progress of your LCD conversion? How the new schematic/PCB does work, if you built it? Could you manage the power supply from J5 connector of the scope board?

In your first schematic you planned to use some signal level shifter, which you changed to serial resistors as I can see. Does this work safely with the FPGA? How did you calculated the necessary resistor value?

Do you power the FPGA in your setup from the RAMDAC? On the schematic I can see that +5V is connected to J6 and also to J8 (which goes to FPGA), so I assume you power the FPGA from RAMDAC pins. Am I right.
What about the 3.3V, do you use external power supply for this?

Thanks,
Laszlo

[TerrySt]

Laszlo,

I am also looking into using the excellent vhdl code from Vincent.  I have a TDS 524A that I want to convert to LCD, so I have been looking into some of those same questions.

For the level shifter, I think it depends on the FPGA you intend to use.  The older versions apparently have clamping diodes on the inputs to prevent the input level from rising more then one diode drop above the VCC for the IO bank of the FPGA.  So the resistor just limits the input current to the pin .  (5V - 3.3V - 0.6V )/ 330 Ohms = 3 mA into the pin, which is a safe current.  But I think the newer FPGAs do not have the clamping diodes.  I can't find any proof of that in the data sheets, but I found a discussion that said they dropped the clamp diodes in favor of having hot swap capability on the inputs.  The resistor value is a compromise between being high enough to limit the input current but not so high that the slew rate of the signal is slowed too much.
I am using a newer FPGA (Spartan 7) so I chose to use a level shifter IC.  Also, I didn't like the idea of loading the o'scope logic signals so heavily on the high levels, nor the slowing of the signals that the resistor would cause.  It probably works fine on an older Spartan, but I prefer a more conservative approach using level shifters (74LCX541D).
I looked at other approaches.  A resistor divider would work (but also loads and slows the signals).  Or the approach used by https://bastelblog.runlevel3.de/en/restore/ds1250-fram-replacement/ uses a red led and a schottky diode on each signal line.  It works well (I built the FRAM board for my scope) and is pretty small and easy to include in the design.
But in the end, I think I will just use the level shifter IC.

For the power supplies, you can probably get away with using the 5V supply from the scope at the RAMDAC chip to power the FPGA board.
But again, I decided to be conservative.  I am planning on using the G065VN01 V2 LCD panel.  It requires 3.3V for the logic at 300mA max (I measured 220mA on mine) and 12V for the LCD backlight at 250mA.  Then you need whatever current the FPGA board you are using will draw.  Mine needs 5V.  The current is probably 200 to 300mA or so, but I haven't checked it while running the full vhdl code yet.
Since I needed 12V for the lcd panel anyway, I decided to use a small smps powered from the 25V at the connector on the oscope that was used to drive the CRT power supply.  That gives me 12V in a small package (OKI-78SR-12/1.0-W36H-C, DigiKey 811-3294-ND).  Then I used the 5V version (OKI-78SR-5/1.5-W36H-C, DigiKey 811-2692-ND) also powered from the 25V o'scope supply for the FPGA board  The FPGA board converts the 5V to the 3.3V and 1.8V for the Spartan 7.  I added a 3.3V linear regulator (TLV76133DCYR) driven from the 5V switcher to supply the LCD logic and the level shifters.   This is a bunch of overkill, but it doesn't add much expense.
The nice thing about the new version of the LCD panel is that it uses LEDs for the backlight running off 12V.  The older version required a high voltage inverter.
Unfortunately it changes from a parallel data input to a four channel lvds serial input.  I had planned to use the FPGA to drive the lvds signals, but I could not find a cheap FPGA board that allowed the power supplies to the FPGA to be set so that lvds signaling could be used.  So instead I an using SN65LVDS1DBVR chips to convert the 3.3V logic from the FPGA to lvds.

I bread-boarded the FPGA and lvds interface and it works fine.  I have now made a pcb with all of the circuitry and am working on trying to make it work. 
One problem I've found is that I haven't been able to find a PLCC socket that fits down over the RAMDAC chip well enough to make good electrical contact and stay mechanically attached.  I have purchased several through-hole and smt versions of the 44 pin PLCC socket and none of them work well.  I can see from the photos that Vincent sanded the top of the socket down.  That helps some.  Also, you have to remove some small standoff posts from the inside of the socket so that the RAMDAC chip fits deeper into the socket.  Those changes barely work, but there isn't a really solid fit.  I have been working on re-shaping the contacts in the through-hole socket and am able to get what looks like a reasonably good connection.

Another problem I'm having is due to needing a 175MHz clock for the lvds outputs to the lcd.  My plan was to use the 25MHz clock to the RAMDAC and use the MMC module in the Spartan 7 to generate a phase locked 175MHz clock.  When I tried it on the breadboard,  it worked great.  But when I try it in the o'scope, the 24MHz clock is too jittery to get a good phase lock.  It may be specific to the TDS 524A.  The clock distribution on other models is different.  I'm able to get a fairly decent display, but there is some noise and jitter in the display that shouldn't be there.  If I use the 100Mhz clock on the FPGA board instead, it has a good clean 175MHz signal, but since it isn't synced to the 24MHz pixel clock in the 0'scope, there is some ripple in the display.  I'm still trying to come up with a good solution.  It wouldn't be an issue if you use the older version of the LCD that doesn't use lvds (if you can still find one).  And it may be OK with a different model o'scope.  There is something about the clock routing on my o'scope that makes it pick up jitter in the 24MHz clock signal between the oscillator and the RAMDAC.

The vhdl code from Vincent seems to work, although I think the jitter in the clock signal makes it act up every now and then.  I think I will be able to tweak it to make it stable with my o'scope, and if yours doesn't have the excessive jitter in the 24MHz clock, it will probably be fine.

Terry

[ltarjanyi75]

Hi Terry,

Thanks for the information about your project, it is very valuable, since I'm trying to do the same.

I also have a G065VN01 V2, which I could drive by a Spartan 6 devboard. I have not tried to attach it to RAMDAC yet, so you are ahead of me. This jitter issue does not sound promising, but will see what it will be in my case (744A scope). I don't know how, but maybe the HSYNC/VSYNC signals of RAMDAC can be used to provide synchronization on the FPGA.

Regarding FPGA code, Vincent's code is a great help, I more or less understand how it works now, though I have plenty to learn, since it is my first FPGA project.

I also only tried to attach one version of PLCC socket onto the RAMDAC and I agree, that it does not fit correctly. I did not have time to play with it more and to look for other types, because I'm currently focusing on the power board and FPGA board design.

If I'm correct you also plan to build your own FPGA board, which you can directly plug with the socket to the RAMDAC. (And not a ready made FPGA devboard which you fit on a PCB with socket, like Vincent did so far.)

Now I work on the power board, which can be attached to J5 socket of the scope board. It has 5V pins beside the 25V, so you don't need to convert the 12V down to 5V.

Bye,
Laszlo

[TerrySt]

Laszlo,
I started out planning to use an FPGA board (S7 mini) (https://shop.trenz-electronic.de/en/TE0890-01-P1C-5-A-S7-Mini-Fully-Open-Source-Module-with-AMD-Spartan-7-7S25-64-Mbit-HyperRAM).  but I may try doing an FPGA on my own board.  I have been itching to try my hand at some bga soldering.

I'm attaching pictures of what I currently have.  I went with a fairly large board because I wanted to use the two nearby support points in addition to the RAMDAC socket.  This meant using an extra board for the socket that let me adjust the height to match the supports.

[TerrySt]

Back side with  the socket board.

[ltarjanyi75]

Wow, nice design and work! Clever idea with the supports!
What do you plug into that big connector with the strip cable? Is it connected to J5 connector pins?

[Tantratron]

I bread-boarded the FPGA and lvds interface and it works fine.  I have now made a pcb with all of the circuitry and am working on trying to make it work. 
One problem I've found is that I haven't been able to find a PLCC socket that fits down over the RAMDAC chip well enough to make good electrical contact and stay mechanically attached.  I have purchased several through-hole and smt versions of the 44 pin PLCC socket and none of them work well.  I can see from the photos that Vincent sanded the top of the socket down.  That helps some.  Also, you have to remove some small standoff posts from the inside of the socket so that the RAMDAC chip fits deeper into the socket.  Those changes barely work, but there isn't a really solid fit.  I have been working on re-shaping the contacts in the through-hole socket and am able to get what looks like a reasonably good connection.

Hello Terry,

It is great to see first Vincent from France then Lazlo from Hungary and now yourself in USA trying to come up with another open source variant for this very topic.

As I've mentionned earlier this year here https://www.eevblog.com/forum/testgear/tektronix-tds744-crt-to-color-converter-fpga-module-diy/msg4639096/#msg4639096, I initially bought in 2021 one kit from Simmcomm labs for my TDS794D. Later french university test center asked me to repair and hack their failed TDS540C then one year later, their mono-CRT failed so I recommended they order same kit to Simmcomm labs. I did made the all repair and installation for them. Then later in 2022 a german customer asked my company for two reconditionned and hacked (one TDS580C and one TDS784C). Same story where I suggested them to order 2 kits from Simmcomm labs but they ordered 3 kits, they offered me as an extra payment one kit which I've later installed in my TDS784D.

Personnaly I'm more a radio guy and digital signal processing guy so digital video processing, I do not know very much but find interesting. Anyway, I still use two Simcomm Labs LCD-TFT kits, they work fine except in my opinion the low contrast quality of the G065VN01 V2 LCD panel. Ideally going after OLED or another brand would be a plus but again, the commercial kit works. The onwer of Simmconn lbas told me it is impossible to beat the contrast of NuColor tektronix technology so it is a choice of lower consumption, lighter weight, less failure to go with LCD-TFT medium visual quality.

Reading part of your post suddenly brings some explanation why it was hard for me to install the QFP socket onto the U199 chip. It is very tricky installation, can get loose in no time depending how you press it. No idea what part number Simmconn labs is using but I wonder if they did not sand it partially but for sure, I'm not trying to remove it to install later unless really needed (i.e. main PSU repair). The removal from J5 is no problem of course, the PLCC-44 reverse socket paradigm really is very wierd.

Now legally I'm wondering what this sentence means, namely in my invoice slip which I've paid to Simmcon labs. It is written The Xilinx FPGA design in the NewScope-5/6/7/8/9 kit is released under GPL 2.0 licence, which means that you have written offer to receive the source code of the FPGA design. The source code is available upon request. The schematics, PCB layout and firmware remain proprietary

The kits came with 4 electronic parts: LCD panel, the power plug connected to J5, the FPGA plug connected into U199 chip and respective cables. Does the previous sentence voids or makes it illegal to check and communicate the voltage values (i.e. power rails), to reuse the concept of receive power from J5 connector, the paradigm to PLLC-44 connect the U199 chip ?

N.B. I think it will be very hard to beat the price of the kit in USA even though it is quite expensive, my question is really about how far legally some of us can really say redo or improve say a prototype or commercialize ?

Albert

[TERRA Operative]

That GPL 2.0 statement is probably because Simmconn Labs is using a library or code that is also GPL 2.0, so their code needs to be released under the same license.

I wonder if is worth getting the source and checking it for any hints or tricks for us here?

[TerrySt]

Wow, nice design and work! Clever idea with the supports!
What do you plug into that big connector with the strip cable? Is it connected to J5 connector pins?

Yes, it plugs into the connector that was used to connect to the crt power supply before it was removed.  I am just using the 25 volt supply voltage from it, but I’m sure also using the 5v supply would work. 

Terry

[ltarjanyi75]

I wonder if is worth getting the source and checking it for any hints or tricks for us here?

It would be interesting how they handled the sync issue Terry mentioned. However it will be questionable what really they would share with anyone, if something at all.

[TerrySt]

I think the issue I am having with syncing is due to power supply noise or ground bounce on my new board.  I’m still working on it but it looks like the clock jitter is way worse after the level shifters I am using.  Once I fix that, it is easy enough to just use the pll or Mmc module in the Fpga to lock onto the 25 MHz click and generate the 275Mhz clock needed for the lvds signals to the new lcd panel.   

Terry

[TerrySt]

I've been working on tracking down the cause of the clock jitter that is causing noise in the display.  Unfortunately, it looks like it is caused by my decision to use the level shifter ICs to convert from the 5V logic levels in the o'scope to the 3.3V signals needed by the FPGA (Spartan 7).  The chip I was using is the 74LCX541D octal non-inverting buffer.  It was a bad idea for a couple of reasons.  First, I completely ignored the fact that the data bus signals get tri-stated.  That leaves the input to the buffer floating, which is a bad idea.  They will draw excessive current and even oscillate.  I could see signs of that and it caused a lot of noise on the power and grounds.  The other reason is the simultaneous switching of several signals on the same chip.  This would probably be OK for most of the signals, but when the clock is fed through the same chip that has seven other signals all switching at the same time, the clock gets noise introduced onto it that causes jitter.
I'm not sure what I'm going to do instead.  I checked the two methods I mentioned earlier (resistor divider on each line or red LED and Schotky diode in parallel on each line.
The resistor divider slows the rise time as expected.  I used 330 Ohms serial and 680 Ohms shunt.  That degrades the rise/fall times, but would probably work OK.  Those values load each signal line by about 5mA.  Lower values would improve the slew rates, but at the expense of extra loading.
The LED/Schottky approach works better. 
Here are o'scope shots of each approach.  Either would probably work.  Maybe I could use the level shifters for most of the signals and use the LED/Schottky for the 8 data bus signals and the clock.

Terry

[Tantratron]

Hello Terry,

I do not have knowledge on FPGA for digital video neither do I know well the operation of the RAMDAC. However I'm using two LCD Kit from Simmconn labs so I took pictures of the board and quick voltage measurements which I can share later if you need.

The more I think about what is written in his invoice The Xilinx FPGA design in the NewScope-5/6/7/8/9 kit is released under GPL 2.0 licence, which means that you have written offer to receive the source code of the FPGA design. The source code is available upon request. The schematics, PCB layout and firmware remain proprietary. This seems to only concern the FPGA firmware, the FPGA plug or board and probably not the power plug board.

After all, the power plug is not real brain, just board re-using the +5Vdc and +25Vdc rails from J5 connector then generating via LDO and buck regulator 3.3Vdc and +12Vdc. Note that I happen to have pictures of this power plug version 0 from 2014 which obviously was revised version 1 in 2018 so the power generation or conversion from J5 rails could be not obvious unless he was obliged to redesign due to lack of components. Wether using a LDO or buck regulator, all these schematics and pins out are standard and found in many datasheets.

First thing, his FPGA is SPARTAN XC3S50A and the board has a secondary LDO generating 1.2Vdc from the incoming 3.3Vdc (why 1.2 Vdc is needed, no idea).

Second thing, I recommend from a local EMI and EMC point of view to rather generate the 3.3Vdc from 5Vdc instead from 25Vdc -> 12 Vdc -> 3.3Vdc because deep down conversion can sometimes generate lot of interference depending on the PCB layout. Maybe these are some noise corruption affecting your jitter, no idea but there must be serious reason Simmcon labs used both 5Vdc and 25Vdc from J5 connector.

Last thing, in the initial version, both HSYNC and VSYNC were routed from J5 to FPGA, later revision only routes HSYNC but I'm really not certain this signal is important because the key thing is the 24 MHz quartz near U199 chip (ADV471 RAMDAC) receiving the FPGA plug.

Attached some pictures if they can help anybody, just my 2 cents

Albert

[TerrySt]

Albert,
Thanks for the pictures.  Their solution is nice and small.  Very well done.  Mine is much larger since I am using an FPGA dev board instead of an FPGA.  I wanted to use the Spartan 7 and it is only available as BGA.  So at least for my first try, I'm sticking with a dev board so I don't have to solder bga.  I may try to make my own fpga board later.
I don't know why they need to route either hsync or vsync from the J5 connector to the fpga.  I just use the /BLANK signal from the RAMDAC.  It seems to work great.
The socket is interesting.  I purchased what I think is that same socket (Methode p/n 213044601) and it is very difficult to get it to fit over the ramdac and stay in place.  Might work with a very small board like they have but not a larger one like mine.  It would keep popping off.  I've purchased several other brands of socket, and none seem to work well without modification.  The Methode one is probably the best I've tried.

Terry

[TerrySt]

I managed to add the red LED and Schottky diode level shifters in place of the I.C. level shifter on the 8 data bus and the clock lines.  The noise issue is gone and the display is nice and clean.   
I'll play around with it and see if it is stable while I start working on a re-spin of the board.

Terry