SysClk LWLA1034 (and others) FPGA Enhancements

[Scratch.HTF]

I've read at https://sigrok.org/wiki/Sysclk_LWLA1034 that different FPGA bitstreams can be reloaded with Sigrok, and I believe that incorporating the following is possible in the LWLA1034 (and possibly with the LWLA1016 and LWLA2034 which uses the same FPGA) while retaining data compression and State Clock functionality:

* Qualifier capability (record data only on qualifying conditions)
* If-Then-Else sequencer with full conditional structure (up to a certain number of levels) for the logic analyser
* Multiple state trigger words
* Range recognizer
* Selective data acquisition functions
* Programmable STOP conditions
* Option to combine logic ports to extend number of points (e.g. 34-16-8-4-2-1 bit for 256K-512K-1M-2M-4M points) and define segment size
* 64 bit (probably less) FIFO stream trigger (good for triggering on I2C and SPI)
* If possible, enable an option to capture data on either edge (rising and falling edges) of the State Clock

For the host software, there should be an option for automatic retriggering while retaining previously captured data.

[abraxa]

Certainly, there are a lot of things that are possible. Do you intend to work on implementing these features?

[Scratch.HTF]

My strength here is contributing realistic and viable ideas.