Example of why people say you sholdn't use MOSFETs in parrallel as dummy load

[SpottedDick]

Nothing much to say here. Six MOSFETs in parallel as a dummy load. Due to variance you can see two in particular are taking most of the load.

This was just before I put the heat sink on.

(I already had the thermal paste on them, otherwise I would have used back tape to make the image a bit more accurate, but it gets the idea across).

[ebclr]

Some small resistor will help to equalize

[TimFox]

Some small resistor will help to equalize

Best to install equalization resistors in series with the source terminal of each device.

[fourfathom]

The source resistors are a good idea, but remember that the MOSFET RDS_ON has a positive tempco, so the imbalance you are seeing will not be as bad when the transistors are all sharing the same heatsink.

[nctnico]

Some small resistor will help to equalize

Not small. You'll need a considerable resistor value to equalize the currents. MOSFETs have a large variation. And you'll want to use MOSFETs for analog (audio amplifier) applications in order to have a reasonable SOA at DC. I very much prefer to use transistors mainly because the collector already acts as a current sink by definition. At DC you only need to have a slow loop to compensate for temperature drift effects.

[SpottedDick]

Yup, large watercooled heatsink. The temperature variation will be very small and I put my shutdown NTC right in the hotspot of this image, so I'm well protected. I just thought it was an interesting image to share.

[Circlotron]

The source resistors are a good idea, but remember that the MOSFET RDS_ON has a positive tempco, so the imbalance you are seeing will not be as bad when the transistors are all sharing the same heatsink.

The MOSFET RDS_ON does indeed have a positive tempco but that is only useful when all MOSFETs are fully turned on. In that situation it wil help current sharing. When they are only partially on, in their linear region, the gate threshold voltage dominates the situation. It has a negative tempco so it makes the hotter MOSFET dig in harder.

[Caliaxy]

Manually selecting them for matched Vgs wouldn’t hurt either.

[MrYakimovYA]

Hi!

If all MOSFETs are intended for linear mode you should use opamp with negative feedback (and current shunt) to limit current through every transistor. See the circuit diagram any Agilent Electronic Load. There are plenty of information there. In switch (not linear) mode, AFAIK, there is no need neither opamp circuits nor equalizing resistors.

[Scratch.HTF]

I've read that in an ARRL article of a 300-400W 12V power supply, this project uses eight parallel connected 2N3055 power transistors for regulation and that they show unequal current distribution since the transistors came from various sources despite the low value spreading resistor in each emitter and that transistors from a single manufacturing lot should be sufficiently uniform for this application.

[David Hess]

The source resistors are a good idea, but remember that the MOSFET RDS_ON has a positive tempco, so the imbalance you are seeing will not be as bad when the transistors are all sharing the same heatsink.

MOSFET RDS_ON has a positive temperature coefficient in saturation.  In the linear range, the temperature coefficient reduces to zero as the drain-to-source voltage increases and then reverses becoming negative.

Manually selecting them for matched Vgs wouldn’t hurt either.

Grading them for matched Vgs helps considerably and reduces the required source ballast resistance.

The Siliconix MOSPOWER application book has an example showing how to calculate the required ballast resistance for a given Vgs mismatch and thermal resistance.  If the power is derated sufficiently, then no source ballast resistance is required.

[jusaca]

The source resistors are a good idea, but remember that the MOSFET RDS_ON has a positive tempco, so the imbalance you are seeing will not be as bad when the transistors are all sharing the same heatsink.

Wouldn't the imbalance be even higher with a shared heatsink? The FETs that are already carrying a smaller current will get hotter from the shared heatsink and get to a higher resistance. This leads to an even smaller current through these FETs.

[fourfathom]

The source resistors are a good idea, but remember that the MOSFET RDS_ON has a positive tempco, so the imbalance you are seeing will not be as bad when the transistors are all sharing the same heatsink.

Wouldn't the imbalance be even higher with a shared heatsink? The FETs that are already carrying a smaller current will get hotter from the shared heatsink and get to a higher resistance. This leads to an even smaller current through these FETs.

Yeah, probably.  I've already been corrected on this (V_GS negative tempco dominates anyway), but I was reading that (many?) power-FETs are essentially many paralleled drain-source channels on one piece of Si, and in addition to the intrinsic matching it's the positive tempco that keeps the current equally distributed.  But now that I consider this, the only way this works if there is some amount of thermal isolation between channels.  So my heat-sink comment was doubly wrong.

[MK14]

The following app note, seems to shed some light on such a MOSFET situation.  No quotes from it, as there are too many details to easily summaries it.  Without risking confusion.

https://assets.nexperia.com/documents/application-note/AN11599.pdf

EDIT:  But here is a bit, anyway:
From "5. Partially enhanced (linear mode) power sharing".

This behavior is due to the Negative Temperature Coefficient (NTC) of gate threshold
voltage VGS(th). As the group of MOSFETs starts to enhance, the MOSFET with the lowest
VGS(th) starts to conduct channel current first. It dissipates more power than the others and
heat up more. Its VGS(th) decreases even further which causes it to enhance further.
This unbalanced heating causes the hottest MOSFETs to take a greater proportion of the
power (and get even hotter). This process is unsustainable and can result in MOSFET
failure if the power is not limited. Great care is needed when designing paralleled power
MOSFET circuits that operate in the partially enhanced (linear mode) condition

[David Hess]

The source resistors are a good idea, but remember that the MOSFET RDS_ON has a positive tempco, so the imbalance you are seeing will not be as bad when the transistors are all sharing the same heatsink.

Wouldn't the imbalance be even higher with a shared heatsink? The FETs that are already carrying a smaller current will get hotter from the shared heatsink and get to a higher resistance. This leads to an even smaller current through these FETs.

Thermal coupling between the MOSFETs helps to balance the current whether the temperature coefficient is positive in a switching application or negative in a linear application.

In most applications, the effect of differential heating in linear operation is to make the problem worse. One way to minimize the effect of asymmetrical currents is to maximize the thermal coupling between the devices (make Rc as small as possible). This is the same conclusion reached for parallel devices operating as switches!

- Siliconix MOSPOWER Applications, 5.3 Parallel Operation of Power MOSFETs (TA 84-5), Page 5-20

[pqass]

Hi!

If all MOSFETs are intended for linear mode you should use opamp with negative feedback (and current shunt) to limit current through every transistor. See the circuit diagram any Agilent Electronic Load. There are plenty of information there. In switch (not linear) mode, AFAIK, there is no need neither opamp circuits nor equalizing resistors.

That's what I'm doing with my modular load (see attached).  Just stack as many modules as you need such that each is limited to at most 50W or 5A. I plan to mount each on an aluminum plate with standoffs and exhaust fans on an end.    I'm sure I can squeeze the opamp and passives to a in² in my next iteration.

Cable management is easy as you just parallel the spade connectors and P1 pins except for shunt voltage/current readback (pin 3) which is individually connected to an ADC mux input; all pin 4s are fed from a single DAC output.   My shunt is made from 3 twisted strands of 24AWG nichrome wire giving 0R1.  The MOSFET is an IRFP150M.  The opamp is a shitty 4558 (a dual 741) that I salvaged as I didn't have another SOIC on hand. I gave the module a bipolar supply in case a non rail-to-rail opamp is used.

[MrYakimovYA]

That's what I'm doing with my modular load (see attached).

Nice design!

Could I ask you: what about stability of amplifier? Did you simulate the circuit in any SPICE software like LTSpice, Micro Cap and son on? Isn't 10 microfarad capacitor too big in the feedback loop? The circuit could be stable but the bandwidth could be limited to hundreds hertz. So the step response could be a bit slow AFAIK, any electronic load should be as fast as possible in comparison to any DUT (device under test).

[pqass]

That's what I'm doing with my modular load (see attached).

Nice design!

Could I ask you: what about stability of amplifier? Did you simulate the circuit in any SPICE software like LTSpice, Micro Cap and son on? Isn't 10 microfarad capacitor too big in the feedback loop? The circuit could be stable but the bandwidth could be limited to hundreds hertz. So the step response could be a bit slow AFAIK, any electronic load should be as fast as possible in comparison to any DUT (device under test).

My goal was to make a generic (ie. common footprints), repeatable design block; keeping the feedback loop short. Given that there can be many MOSFETs and they each need their own personal space, I thought it best to put the long lines (back to the MCU) on the current set and readback signals and not on long gate leads to a close collection of opamps.

I haven't done any software simulation although I'd like to get familiar with LTSpice eventually (I think it works under Wine for Linux). The cap is probably overkill but necessary (due to past experience with oscillations on another load implementation).  This load is rock-solid at 5A continuous (as seen on my 'scope). 

Out of curiosity, I connected this load to my XANTREX XT7-6 lab power supply (set to 5V, 6A) via 3ft/1m 18AWG wires.  See attached for various waveforms; YELLOW is from my wavegen into the +Vin of the opamp (P1, pin 4) and GREEN is the shunt voltage/current readback (P1, pin 3) signal.  The first screenshot is a 570mV, 2Khz, square wave signal.  The second is the same but at 20%; pulsewidth is 100us wide.  The third is the same as the second but zoomed in.   A continuous 570mV produces 5.00A on the display of my PS.  The 50% signal shows 2.50A, and the 100us pulse shows 1.00A.

As you can see the GREEN is slow to ramp up.  Also, that negative edge spike! It could be my PS. I'll try another to see if it's still there.   I can always substitute a better opamp, smaller cap/resistor, another MOSFET.  Now I have something I can experiment with.  On the whole, I'm happy with this eload so far.

P.S.  The other day, I substituted a 10R shunt instead.  With a the simple analog pot control (see attachment in my last message), the eload was now capable of  0 to 120mA with 1 mA resolution.  I used it to test a salvaged DVD blue laser.  It was very cool seeing the light output ramp up at 30mA to 45mA (where I stopped).