Features look good on paper.
Has anyone tried the logic analyser for SPI and I2C decoding etc
Channels: 16 (shared)32)
Sample rate (real time): 100 MSPS
Buffer size/channel: up to 16K samples33)
Input logic: LVCMOS (1.8V/3.3V, 5V tolerant)
Multiple trigger options including pin change, bus pattern, etc34).
Cross-triggering between Analog input channels, Logic Analyzer, Pattern Generator or external trigger35).
Interpreter for SPI, I2C, UART, Parallel bus36).
Data file import/export using standard formats37).
36 This functionality is implemented by WaveForms software in the PC, using the buffered data from the FPGA. After a acquiring a complete data buffer at the FPGA level and uploading it to the PC, the data is processed and displayed, while a new acquisition is started.
Thanks Joe