I am a technical support engineer from Siglent, and so glad to offer effective technical support
I do have question for you: by comparing latest models with and without "long memory" i recognized that
these without long memory are using only 4 (dual) ADCs instead of 5 (dual) ADCs as on long-memory enabled models.
I know how both works, and know that both ways have pros and cons:
4ADC + less interleave distortion due better ratio of clock jitter on non-dedicated FPGA clockout pins
vs. phase shit needs for 1GSs and amount of ADCs.
- higher gain distortion due overclocked ADC (125MHz instead of 100MHz on each channel)
+ costs (one less chip)
5ADC - more interleave distortion due worse ratio of clock jitter on non-dedicated FPGA clockout pins
vs. phase shit needs for 1GSs and amount of ADCs.
+ lower gain distortion due overclocked ADC (125MHz instead of 100MHz on each channel)
- costs (extra chip needed)
My question is actually why both ways? I mean if 5ADCs solution was working for years the change to 4ADCs can be
only price driven, no problem here to understand it, but when that's the way why only (i found it on 200MHz model,
so not the cheapest one) models without long memory are using 4ADCs?
Or maybe my pictures from models with long memory (here CA_M_110300 / SAT7.820.681K) are simply outdated ?
and Siglent is using everywhere 4ADCs (like on the pictures of CA_M_111000 / SAT7.820.681O with no long memory).