Hi John,
short answer to the question regarding SDG2042 (2122) against SDG1032.
I‘m dealing thisdays with my NOS schottky TTLs and a 65 MHz OCXO ( now VC)
to design a by-13-divider with my available ICs to bring it into suitable frequencies to
follow the GSPDO path
The multisim simulation shows a problem above 50MHz I can not there identify.
For a breadboard design test it‘s helpfull to have the SG that goes easy above 60 MHz.
So this is for me the first advantage of my decision for the better and little bit more expensive SG.
And with the SDS as well
For testing on breadboard I built these simple probes:
http://nihtila.com/2019/03/16/tip-3-robust-high-bandwidth-passive-diy-probes/
I used selected 1k (0.1%) resistors and than the selectable divider factor (21) of the SDS inputs with 50 ohms
was first time used and appreceated.
btw: do you have a schematics of your MK2 design by the hand?
I see your need for a function generator with a wider than 65MHz BW but the SDG2000X series max out at 25MHz for square waves so you'll obviously be using the sine wave output for your tests. If you look at the MK I's circuit diagram, you'll note the use of a 74193 to divide by 13. In this case I had to double the 13MHz to 26MHz just so the 2MHz output met the minimum clock input frequency requirement for the final times 5 clock multiplier used to generate the 10MHz locked to the 13MHz OCXO's output.
Even so, I had to select my 74193 carefully to get this to work at all (none of my HC193s were good enough for this job - believe me, I tested my whole stock of HC193s before resorting to the old skool 74193 - hence the 16 pin dip socket on the board).
Whereas I've had to double up to 26MHz to satisfy the clock multiplier's minimum input frequency requirement, you're going to have to divide that 65MHz down to a more manageable 32.5MHz before feeding it into your divide by 13 modulo N counter for a 2.5MHz output you can multiply back up to the required 10MHz (I hope you have a reasonable quantity of '193s to pick from
). After my own experience with the MK I, I'd recommend against dividing a 65MHz OCXO output down to 10MHz for GPSDO use other than as a "Fun Learning Project" (fvsvo "Fun").
I suspect the issue with the multisim simulation was it recognising the input clock speed limits of the 74S logic family. I tried to look for a datasheet on a 74S193 to check this but I don't think any '193s were ever manufactured in this logic family. Even so, I suspect even a 74S193, if any ever existed, would struggle with such a high frequency input clock as 65MHz, hence my suggestions above.
Until around 18 months ago, I didn't know that any other type of 10:1 and 20:1 passive probe than the classic "Low impedance" type described in that article even existed.
These new fangled High impedance 'scope probes rather disturbed my engineering sensibilities when I first came across them with my first modern DSO purchase
. Anyway, I've gotten over the shock (of the new) now. They're fine for the job as long as you keep in mind that a 200MHz rated Hi-Z 'scope probe is only good for a 10MHz or so bandwidth when switched to 1:1 (x 1 position).
Since I'm now expecting to take delivery of a bunch of FTDI232 adapters this Monday, I won't be cannibalising the MK I for its FTDI module this week after all. It
is scheduled to be dismantled to recycle its components back to my spares bin - in a week or two's time, just not this week is all.
JBG