back on my silly gen for few minutes...
the cpu is a STM8S103K3 (16 MHz)
and it used a CPLD Altera Max II for driving 8 bits waveform and i guest all other stuff it can do...
there is a clock, seems an 34.546 MHz, might by the clock for the CPLD generator... maybe...
so if i suppose it is true, 34.546MHz is near 29 nSec,
it could explain the jitter in a way to resync the waveform by adding or removing one sample
in a way to have a near correct global frequency waveform.
so it might not be that bad, but i will really prefer a more greatter output frequency, so the
adjusting jitter is less present ...
i might have been interested to keep it has an hackable toy but i don't know if STM cpu and CPLD Altera can
be locked. if it is the case there no fun there ...
anyone had hack their SG1005 ?