open source GPIB adapter

[dazz1]

Hi
OK I have made those changes.
I should add a cap to the second gpib connector but that would mess up my text layout. 
I don't intend fitting the C/R, unless I have to.

[Kean]

I don't intend fitting the C/R, unless I have to.

Nope, C/R not really needed.  Just leave shield connection intact through the cable and keep it separate from logic ground, and obviously use the logic ground for the LA/scope connection.
It doesn't hurt to have the 1M resistor between shield and ground as you have it, but that may also already exist in one of your other devices on the bus.

If you have extra PCBs/connectors than I'd be happy to contribute some $ towards one or two and the cost of postage to Sydney.
I have a bunch of GPIB/HPIB gear in the office lab and at my home, spread across several benches, and with some still needing repairs.

[dazz1]

If you have extra PCBs/connectors than I'd be happy to contribute some $ towards one or two and the cost of postage to Sydney.

I was planning on selling the spare ones on the local auction website.  I know  there are a few people watching my blog posts.  It will be easy enough to send one over the water. 

I am also looking at putting the pcb design into pcbway projects.  Mine would be the only project on pcbway that includes "gpib" so I am probably about 30 years late in designing a break out board.

I try and do pcbs in batches to reduce shipping costs. I may be a while before I am ready to get them made. 

[dazz1]

Hi
OK I have settled on a final version of the gpib breakout board.

The most significant change is the addition of notches that are almost mounting holes.
I usually include mounting holes, but I think if anyone makes one of these, they are unlikely to make an enclosure.
If they want to 3D print an enclosure, they can include keys in the print to match the notches, or
they can use M3 screws.

I have refined the text on the silk screen to make it easier to use.  It should not be necessary to refer to standards or pinouts to use this board.

[tautech]

Test is it ?
Unconnected NET pin 1 J3. 

[dazz1]

Test is it ?
Unconnected NET pin 1 J3. 

No not quite.  The pcb is correct.  That pin, and the one on the other header are "V" on the HP logic analyser 40 pin pseudo standard.  "V" is not connected on my scope.  So this connection would only be active if a HP LA was connected, and the other header was connected to something that needed "V". That is extremely unlikely but it didn't cost anything to add the track, and the other LA signals not used by the scope.  So all good.

Also pin 5 is NC on the HP standard.

Edit: On closer inspection, the line indicates the "J3" label is linked to the connector, because I had selected the J3 label.  So no problem but well spotted.

[tautech]

Test is it ?
Unconnected NET pin 1 J3. 

No not quite.  The pcb is correct.  That pin, and the one on the other header are "V" on the HP logic analyser 40 pin pseudo standard.  "V" is not connected on my scope.  So this connection would only be active if a HP LA was connected, and the other header was connected to something that needed "V". That is extremely unlikely but it didn't cost anything to add the track, and the other LA signals not used by the scope.  So all good.

Also pin 5 is NC on the HP standard.

Edit: On closer inspection, the line indicates the "J3" label is linked to the connector, because I had selected the J3 label.  So no problem but well spotted.

Not what I spotted.....the little arrow on the Pin 1 trace that the ratsnest link connects to.
I believe with your editor this indicates a not fully terminated NET.

[dazz1]

Not what I spotted.....the little arrow on the Pin 1 trace that the ratsnest link connects to.
I believe with your editor this indicates a not fully terminated NET.

It's a warning about pin 1 pad attributes not matching the symbol.  Not an open net and not a problem.

[dazz1]

Hi
I have shared my GPIB breakout board on PCBway here:
https://www.pcbway.com/project/shareproject/GPIB_Break_Out_Board_f7812b3e.html

I have order parts for 5x boards, because of MOQ's so I will have 4x for sale.

[dazz1]

Hi
I have edited this post  because I have made a new version 2.0 of the GPIB breakout board.  I have scrapped the version 1.0 boards.

The version 2.0 has the termination network required by HP for digital inputs.  The resistors and capacitors on each signal line are SMD fitted between the pins of the headers.  These pins provide some physical protection for the components to stop them getting knocked off.  The capacitor/resistor are stacked to keep the pcb design simple and neat.    There are 3 smd components but it looks like only 2 in the photos.

This breakout board allows direct connection to an HP logic analyser, I don't have, or my HP54645D oscilloscope. 
The other header provides direct connection to all of the raw GPIB signals.    This allows for an adapter to be made for another instrument that is not an HP.

I have shared my version 2.0 GPIB breakout board on PCBway here:
https://www.pcbway.com/project/shareproject/GPIB_Break_Out_Board_f7812b3e.html

I have made the first two version2.0  GPIB breakout boards.
I only need one breakout board and I have a bag of parts I don't need.  I could make up a kit set to sell if there is any interest.

[julian1]

Thie attachment shows the ethernet to GPIB adaptor that I use (sitting ontop of the inevitable HP box). As you can probably see this one was hand soldered (!)  The central LQFP-144 is the STM32F439ZET6 and the SOICs to right the bus drivers. Voltage regulators on left and the ethernet PHY chip is on the underside.

This looks pretty interesting.
What part was used for the two transceivers? I count 20pins so perhaps 75ALS160/75ALS161 for 48mA drive and electrical compatibility with the ieee-488 standard.

Was the code ported from the AT-megato the stm32f4?
Perhaps the schematics/ footprints are hosted on github/gitlab?