SDS1202X-E Trigger Serial doesnt work?

[STM55]

Hi! I cant trigger spi signal (1 burst in 2 seconds)
Latest firmware 1.3.27
Spi in: mode 3
Data sent: 0xF0
Trigger set to -> serial
data : 8
Clock:CH1: edge:falling treshold 1V
MOSI:CH2 treshold 1V
bits set to: xxxx xxxx
order: MSB

Auto semms to give short blip on screen, normal mode does nothing, single mode does nothing.

I can trigger this signal in trigger: edge, it looks ok.

Edge:

[tautech]

Seems obvious you have data that isn't coinciding with the clock. 
No wonder a Serial trigger is confused.

[nctnico]

Buzzz. Wrong answer. That data looks just fine. Keep in mind that with SPI data can be send/captured on rising or falling edges. In this case data is sent on rising edges and captured by the device on the falling edges.

The right answer is likely that just like serial decoding, SPI decoding got messed up as well on a recent firmware release on this oscilloscope. The OP can try to downgrade to a previous firmware version to see if that works.

[tautech]

Buzzz. Wrong answer. That data looks just fine. Keep in mind that with SPI data can be send/captured on rising or falling edges. In this case data is sent on rising edges and captured by the device on the falling edges.

Data is Ch2, and about 4 clock cycles of it are before the active the clock period.
Something is wrong with the OP's setup.

[ebastler]

Data is Ch2, and about 4 clock cycles of it are before the active the clock period.
Something is wrong with the OP's setup.

It should not matter what the data line does before the clock pulses start. There is valid data while the clock ticks, and it does represent the intended value of $F0, sent MSB first.

However, it looks like the data line changes exactly on a falling edge of the clock. If that is meant ot be the active clock edge, there may be an ill-defined state at that point. (If a hold time is required after the edge -- not sure whether that is the case?)

[2N3055]

SPI supports 4 modes.

Mode 3 is clock idle state high, sample on rise edge, clock out on falling edge.
So data edges will be in synch with clock falling edge, and sampled on next rising clock edge.

Most commonly used mode is mode 0. Means clock is idle low.
When you use CS too it is obvious what framing is. You only need to set what clock sampling edge is.
With only 2 ch used, you need to set framing by timeout.

for mode 3 you need to set clock rising and set proper timeout

[2N3055]

Just a note.
Useful practice is to set decode first with single (or about one) data frame captured by using single edge trigger. You set decode setup to the point it decodes right. Then copy setup to trigger.
That way you have verified the setup beforehand.