Scope Current Probe Deskew Fixture PCB Project

[steve1515]

After some discussion with the members over on the Siglent SDS2000X Plus (https://www.eevblog.com/forum/testgear/siglent-sds2000x-plus-coming/) thread, I decided to try and make my own deskew fixture PCB with adjustable frequency and rise time. The adjustable rise time is to account for differing inductance since the current loop would be a wire added to terminal blocks and not part of the PCB. This would allow for varying numbers of turns. I've drawn up the following schematic. It works well on the bread board, but I wanted to post here for others in case they were interested. 

[Martin72]

Hi,

First question, why adjustable frequency ?
Because of the limited bandwith of some probes ?

[steve1515]

Hi,

First question, why adjustable frequency ?
Because of the limited bandwith of some probes ?

Yes, that was my thinking. I wanted it to work with more probes... even cheaper ones that don't have high bandwidth.

[tautech]

It works well on the bread board........

Interested to see some current probe captures with it.

BTW, your thread subject would benefit from an edit and the insertion of the word Current. 

[steve1515]

I've updated the thread title. Thanks for the tip. 

I've also taken some screen shots. My probe isn't the best. It's a Fluke i80-110s set to 100mV/A. I have 1k on the gate of the MOSFET and 4 turns of wire on the current loop. If I put about 500R on the gate, there is a slight overshoot but the rise time is about 200nS. Are these on par with other deskew fixtures?

[tautech]

If I put about 500R on the gate, there is a slight overshoot but the rise time is about 200nS. Are these on par with other deskew fixtures?

Voltage/current rise times need to be fast enough to measure the propagation delay differences between a voltage and current probe and if 200ns is indeed the measured rise IMHO it's too slow.
I think faster is better as it allows us to confirm the risetime of a current probe meets spec.

So sure you might achieve 5ns but few current probes are that fast anyways.
IIRC my 60 MHz Tek P6021 has ~7ns spec.

Later I'll check RT of the Siglent deskew fixture.

[steve1515]

I tried it with a shorter wire (1-turn) and a 150R resistor at the gate and I get about 85ns rise time. I eagerly await to find out what the Siglent fixture has for rise times in both of its loops.

[tautech]

2 data points for you.

Voltage probe on the test point of the current loop.
1 turn 147mA loop



8 turn 125mA loop



Your 85ns RT looks to be in the right ballpark. 

[steve1515]

I've updated my schematic to simplify it a little bit and also have a 3D render of my board. What do you guys think?

[Martin72]

Looks good so far. 

[tautech]

I've updated my schematic to simplify it a little bit and also have a 3D render of my board. What do you guys think?

I'd suggest additional USB footprints for the 5V supply.

Plain old USB-B as most of us have plain A-B cables lying around that came with our instruments.

[Kean]

An alternate power connection seems like a good idea.  Micro USB is convenient I guess, but I also like having a convenient way to power things off a lab supply.

I see you changed from 2 x 10R 2W resistors in series, to a single 20R 2W resistor.  What footprint is that?  It looks huge compared to the DPAK, so guessing 4527?  A bit harder to source?

[Jay_Diddy_B]

Hi,


Assuming 50% duty-cycle.

Dissipation in R4

0.5 x 2.5 x 2.5 / 20 = 0.156W (no need for a 2W resistor)

Dissipation in R3 = 0.5 x (2.5² + 5²) /20

= 0.78W

I would use 5 x 100 1206 in parallel.


+1 on alternative to the USB for power (too fragile) add alternative in parallel.

Regards,
Jay_Diddy_B

[tautech]

The resistors in what we are copying this from, the Siglent deskew fixture do get warm but not very warm.

This is the unit in this pic however as it's nearly 5MB  I'll only link the post here:
https://www.eevblog.com/forum/testgear/siglent-sds2000x-plus-coming/msg3142106/#msg3142106

Later a few posts down is Martin's RE diagrams.

[Jay_Diddy_B]

Hi,

I have looked carefully at the high resolution picture that was posted by forum member Martin72. This is what I see from the photo:




I have not drawn the cmos 555 circuits.

I have indicated the power dissipations in the resistors.

I have shown correctly the relationship between the coil, the resistors and the voltage test points.

By connecting the voltage test point to the bottom resistor, this guarantees that the voltage and current are in phase.

Regards,
Jay_Diddy_B

[2N3055]

Hi,

I have looked carefully at the high resolution picture that was posted by forum member Martin72. This is what I see from the photo:

-----------------------------------------------------------------------------------
I have not drawn the cmos 555 circuits.

I have indicated the power dissipations in the resistors.

I have shown correctly the relationship between the coil, the resistors and the voltage test points.

By connecting the voltage test point to the bottom resistor, this guarantees that the voltage and current are in phase.

Regards,
Jay_Diddy_B

Jay,
those are very much correct. Pulse generating circuit is not important. It can even be driven with pulse generator..
Regards,

Sinisa

[Martin72]

This is the unit in this pic however as it's nearly 5MB 

Remember, I´ve promised 2N3055 a hires pic..

[2N3055]

This is the unit in this pic however as it's nearly 5MB 

Remember, I´ve promised 2N3055 a hires pic..

And as a man of honour, you kept it!!

[_Wim_]

I've updated my schematic to simplify it a little bit and also have a 3D render of my board. What do you guys think?

I would connect your voltage header just above R4, as this is more representative for the current actually going through the coil during the turn-on and turn-off of the FET.

[_Wim_]

Green trace: deskew voltage out (short coax)
Blue trace: deskew voltage out  (scope probe 10x) => 8ns slower!
Red trace: Pearson 411 passive current probe (same short coax length as green trace) => no measurable delay
Yellow trace: Fluke I50A current probe => 17ns slower

Test Fixture: 12ns rise time, 18ns fall time
Remark: Pearson has slower rise time as bandwidth is only 20Mhz vs 50Mhz for the fluke probe.

[Jay_Diddy_B]

Hi,

Given the results from _Wim_ it looks like a rise and fall time in the 10 -20ns are is required to deskew the probes.

I would suggest selecting the MOSFET carefully. Do not oversize the MOSFET this is will slow it down.

You are looking for low gate charge.

The RDS(on) could be 1 .

Regards,
Jay_Diddy_B

[Ribster]

So i've made a design based on wim's prototype.
I holds USB C input of 5 volts, also a connector for wired 5V0.

The mosfet is a GaN mosfet with high switching parameters (EPC2014C)

I also put in a selector switch for the internal oscillator with the NE555, or selection for an external clock.
The clock input is fed via an inverter to a mosfet driver to switch the mosfet as hard as we can.

Will order today and post with the results later

[steve1515]

Thanks for all the great suggestions!

I wanted to update everyone on my project. For this revision, I'm going to leave it with just a USB micro input. I waffled on the power input for a long time. In my case, I usually have a USB micro cable around vs other cables and I wanted to use this board as a learning experience for trying to place some parts I haven't used before.

I did modify the voltage reading to be after the coil as Jay_Diddy_B and _Wim_  mentioned. Good catch!  I'm a little embarased that I missed that. 

The large resistors are WSC4527's from Vishay. I ended up with those by reviewing the Agilent U1880A fixture. The were pretty easy to source for me.

If I do another revision, I'll likely change it to the 1206 resistors in parallel and add an alternate power input as that does make sense. I also like the idea of a pulse input!

_Wim_, what FET did you use to get such fast rise times?

_Wim_ and Ribster, would you be able to post schematics of your projects?

[Jay_Diddy_B]

Hi,

I would suggest looking at the BSS316N MOSFET. This is in a more friendly SOT-23 package.

If I compare gate charge:

BSS316N




EPC2014C





The BSS316N should be faster with the same gate drive.

Hot loop

Also watch the layout. The 'hot loop', where the high speed currents are is from the 5V supply to the ground connection at the bottom resistor. The decoupling should be optimized for this loop.




Regards,
Jay_Diddy_B

[_Wim_]

_Wim_, what FET did you use to get such fast rise times?
_Wim_ and Ribster, would you be able to post schematics of your projects?
(Attachment Link)

Hi, I used just some parts I had in my parts bin. The FET is an FDS4559 (N-channel used, complementary P-channel unused) driven by an abused 74LCT2524 clock driver (is a 3.3V part, but I am running it at 5V...)

Attached is a schematic (made in Microcap 12), but clock driver is not shown as that part was not available in Micro-cap and I was too lazy to add it. A very crude drawing of the prototype layout is also shown, as is the Micro-cap simulation file.