SainSmart DDS120 & DDS140 USB Oscilloscope

[coromonadalix]

@bianchifan

Did you check for probe calibration compensation  , a small adjustable capacitor in the base bnc connector of the probe

I had this problem before, badly calibrated probes were messing measurements, and had poor results in voltages.

[bianchifan]

I would return it, this device is pretty much out of spec.

OK, at least I did so.
NO answer from Amazon, nothing...but wait.. since 2 days they are offering a warehouse DDS140

Meanwhile I checked my new DDS140 and this device seems ok.

The two probes are of the model TP6100, which when sold separately reportedly cost $9 on eBay. They are probably not true 100MHz probes, but one review of them that I saw referred to them as "good stuff".

IMHO the probes are "bad" stuff, I wasn't able to calibrate the 1kHz rectangle correctly.
With my TP6100 probes all is fine in 1:10 position.
USB voltage is measured at around 4.9V, fine also.
At the moment I hope to work with.

[doctormord]

DDS140 V1.4

Not working anymore. 

[bianchifan]

DDS140 V1.4

Not working anymore. 

It works for me, just even tested.

Nevertheless an alternative:
https://mega.nz/#!pgdHHQIY
_________________

I wonder about the options 5V/div and 2V/div..IMHO they are nonsense
Feeded with Voltageges about 6V or more will cause the scope to strike.
A red line will be displayed combined with loud beeping.

[merbanan]

@doctormord can I get you permission to upload your image of the DDS120 pcb to the sigrok wiki website ? Earlier this week the Hantek 6022BE got supported with a driver and a firmware. I would like to extend that to support the DDS120. Right now I want to  document the hardware first.

[doctormord]

@merbanan,

You have my permission.

Just link back to "360customs.de".

Regards.

[merbanan]

Ok, I have now added:

http://sigrok.org/wiki/SainSmart_DDS120

For the record here is the Hantek 6022BL sigrok driver:

http://sigrok.org/gitweb/?p=libsigrok.git;a=tree;f=src/hardware/hantek-6xxx;hb=f2a66a8ee669df5afa1b7bdade6e25ac0857fe4b

And then the more interesting part the firmware:

http://sigrok.org/gitweb/?p=sigrok-firmware-fx2lafw.git;a=commitdiff;h=189db3d41e4c3d8a4aec5ec605c03df75577d531



So from reading the thread I have come to the conclusion that the Hantek and SainSmart are fairly similar but there are vital differences that will hinder the use of the Hantek firmware directly.

To start with how does the gain stage work ? What pins control that ?

[doctormord]

If i remember correctly and from the pictures:

PE3 = Channel A AC/DC via Photomos; enabled Photomos bridges AC input cap
PE0 = Channel B AC/DC via Photomos; enabled Photomos bridges AC input cap

PC1= enables Channel A compensation Network
PE1= enables Channel B compensation Network

I'm not sure if it is always enabled when doing AC coupling.

PC2 + PC3 = selects Channel B gain
PC4 + PC5 = selects Channel B gain

PB7-PB0 = Channel A 8bit input D7(MSB)-D0:
PD7-PD0 = Channel B 8bit input D7(MSB)-D0:

[merbanan]

PC1= enables Channel A compensation Network
PE1= enables Channel B compensation Network

I'm not sure if it is always enabled when doing AC coupling.

PC2 + PC3 = selects Channel B gain
PC4 + PC5 = selects Channel B gain

What is a compensation network (when would the firmware enable it) and can you clarify Channel B gain (it's there 2 times)?

What bits correlate to what gain ?

[doctormord]

The compensation network is right beside the white BNCs. I'll have to overthink it.

Edit: Compensation is always active, see schematic.

The gain stage were discussed here:

https://www.eevblog.com/forum/testgear/sainsmart-dds120-usb-oscilloscope-%28buudai-bm102%29/msg535341/#msg535341

It's a 2 stage approach. -6dB and -20dB on the first stage. The second stage is then doing the gain by 3 different resistor values switched into the feedback loop.

So there is:

First stage (Attentuator):
PC1: 0 = -6dB, 1 = -20dB
PE1: 0 = -6dB; 1 = -20dB

and can you clarify Channel B gain (it's there 2 times)?

Sorry, typo, it is:

PC2 + PC3 = selects Channel A gain
PC4 + PC5 = selects Channel B gain

[doctormord]

Wow, long time since i where in the circuit.

As "psynapse" pointed out here:

https://www.eevblog.com/forum/testgear/sainsmart-dds120-usb-oscilloscope-(buudai-bm102)/msg535995/#msg535995

with the internal switch resistance, its going like this by combination of bits.

OK I have looked a bit more at the circuit and the internal resistance of the 4052 is critical.  Allowing internal resistances of 380,500 or 400 ohms for the three states,  Q2 is programmable to have a gain of 2,3 or 5 (1+(620+380)/1000), (1+ (1500+500)/1000), (1+(3600+400)/1000)

Odd gain figures, except we are driving the ADC differential, the other side being 1, the output of the unity gain buffer.  So what the ADC sees is 2-1, 3-1 or 5-1  .... aka 1,2,4  .... It is kind of sweet in a chear cost cutting sort of way.

A quick LTspice confirms


So in summary, J3 is giving divide by two or divide by 10 (and if the divide by 2 is diode clamped, de facto divide by 10 is too)
Whilst J9 gives multiply by one, two or four

Put both together and you have, for the front end gain

x2
x1
x0.5
x0.4
x0.2
x0.1

So to sum this up:

#Channel A:
PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB

#Channel B:
PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB

[merbanan]

This is the function I need to re-implement for the SainSmart

http://sigrok.org/gitweb/?p=sigrok-firmware-fx2lafw.git;a=blob;f=hantek_6022be.c;h=8a73cc07b4ac74828f5303e1f1b7861dd1149cca;hb=189db3d41e4c3d8a4aec5ec605c03df75577d531#l190

With your latest info it will be straight forward. The only thing left is to figure out how to address the PEx pins and implement a new command for AC/DC coupling. And how to output the square wave pulse.

[doctormord]

I wonder if clock setting is working, as the DDS120 is using the IFCLK output:

Regarding the EZ-USB Technical Reference Manual:

http://www.cypress.com/?docID=48811

page 125, the IFCLK can only output 30/48MHz from its internal source. (I must review the trace at IFCLK and CLKOUT.)

Maybe its like:

24Mhz crystal -> PLL (48Mhz) -> /2 divider -> 8051 Core + CLKOUT [pin out] (24Mhz) -> IFCLK [pin in] + ADC_CLK (24Mhz)

Then the 8051-Core, FIFO, and ADC are running at 24Mhz at all time. Sampling is then done by 1/1 (24MHz), 1/10 (2.4MHz), 1/100 (240kHz).

From the specs, this scope should do 50Msps, but only when using both channels - single channel is 25Msps. This can't be true with a 24Mhz clock-source in no way, so we'll end up at 24/48Msps like Hantek. Even the software is lying to us when showing "50MHz" (should be "48MHz" -> 24MHz x 2 Channels)

Conclusion:

50Mhz -> 48MHz == 24MHz x 2 Channels = 24Msps per Channel
2.4Mhz == 2.4MHz x 2 Channels = 2.4Msps per Channel
240kHz == 240kHz x 2 Channels = 240ksps per Channel

The lower samplerates just skip sampling by 1/10, 1/100. 

[doctormord]

It works for me, just even tested.

Nevertheless an alternative:
https://mega.nz/#!pgdHHQIY

Needs the mega decryption key. 

[merbanan]

I wonder if clock setting is working, as the DDS120 is using the IFCLK output:

I just assumed it used the same as the Hantek.

Tracing the pin on
http://sigrok.org/wimg/d/d8/Hantek_6022be_pcb_top.jpg and http://sigrok.org/wimg/0/05/Hantek_6022be_pcb_bottom.jpg it looks to me it is connected the same as the SainSmart. (The signal goes through R35 and on both sides of the pcb and under the chips).

[bianchifan]

Needs the mega decryption key. 

2nd file is from a private account, don't know the problem..
Mega never stressed me , neither Ubuntu(64) nor win7(x64).
No idea, Zippyshare doesn't work for me since some monthsss#

BTW..PCB of the actual DDs140 shows much better soldering job

Ok, I have now added:

http://sigrok.org/wiki/SainSmart_DDS120

Please don't forget DDS140

Until now I thought Sigrok/Pulseview isn't a scope SW but Logic analyser, I used it a few times with my USBee clone from BG.

[merbanan]

Please don't forget DDS140

Until now I thought Sigrok/Pulseview isn't a scope SW but Logic analyser, I used it a few times with my USBee clone from BG.

Well Sigrok hasn't a scope yet. But it provides an api for it. So write one scope app and you can support all the hardware that sigrok has drivers for. And regarding DDS140 support, start by documenting it in the Sigrok wiki. There is lots of information spread around in this thread that could be used to create a wiki page.

[merbanan]

I created a firmware based on the Hantek 6022 one and tried to load it. The controller wouldn't re-enumerate because the fx2 had already loaded a firmware from the eeprom. I then removed a jumper on the board and then the fx2 was happy to load the image. Through the firmware seemed running the values from it was bogus.  I could just hack the eeprom so it wouldn't read the firmware from there I feel that it is much easier to write a driver for the Sainsmart and let it load its own firmware that should be working fine.

[doctormord]

You could program the sigrik firmware to eeprom as well, so it works out of the box, I guess. Flashing the EPROM is shown in this thread, also hex editing the IDs (vendor/class/usb).

For the bogus values, maybe the ADC is read out/running in a different way than on the Hantek?

[bianchifan]

Another try, anonymous on filehorst.de(germen), checked twice from different requesters

DDS140.7z

[merbanan]

You could program the sigrik firmware to eeprom as well, so it works out of the box, I guess. Flashing the EPROM is shown in this thread, also hex editing the IDs (vendor/class/usb).

For the bogus values, maybe the ADC is read out/running in a different way than on the Hantek?

Yeah I know I can modify it, but I want it to be usable without modifications. So unless anyone knows how to reload the FX2 firmware via a usb command I will just implement the SainSmart protocol for sigrok. The bogus values are definitely from differences in the hardware.

[doctormord]

Alright, the commands/functions can be seen from their .dll.

AiReadBulkData
AutoMeasurement
 BufferInit
DataPreDisposal
DeviceClose
DeviceOpen
EventCheck
GetBuffer4Read
GetBuffer4Wr
GetData
GetHWbufferSize
GetInfoByte
GetInfodouble
GetRawData4Read
SetData
SetInfo
SetReadEnableOrNot
SetStableEnableOrNot
SetTrigInfo
TrigDataPrepare
USBCtrlTrans
USBCtrlTransSimple

[merbanan]

I have been working on the sigrok driver and it is sort of working now. I also figured out how to upload custom firmware and get that running properly.

I also found out how to program the extra gain mode that is there but not used by the vendor software.

Now that all this is working I'm hitting the transfer limit of the "50MHz" mode. 240kHz and 2.4MHz seem fine with the exception of the square wave that seem to change the duty cycle depending on the sample rate. So right now I am using interrupt transfers for usb transfers. Is it possible to use something else ? Something faster or is this a limit of the firmware ?

[doctormord]

What's the extra gain mode?

Fastest mode would be fifo streaming. We discussed this in the tread somewhere one the first pages, you may want to look. Problem is, the scope is running blind when transferring data, because of the transfer they implemented.

(The original software is using polling for transfers)

[merbanan]

What's the extra gain mode?

Fastest mode would be fifo streaming. We discussed this in the tread somewhere one the first pages, you may want to look. Problem is, the scope is running blind when transferring data, because of the transfer they implemented.

(The original software is using polling for transfers)

http://sigrok.org/wiki/SainSmart_DDS120 has the details. But channel 0 has 0x0A as valid config and Channel 1 has 0x22. These modes are very close in gain to another gain step. Thus I reason that they omitted it in the software. On your blog you list 5 used modes but in your posts you listed 6. I just sorted out the details which bit to set and found out it was fairly useless.

I think you are wrong about it using polling. I think the 0x33 command is a FIFO clear command. I can at any time just request more packets without any problem. No need to issue a 0x33 command per packet. The vendor software might do it this way to be able to get a clean part of a continuous stream to analyse. They might always get zeros at the start and then a signal to do the analysis on. One of the lower time resolutions only send one 0x33 packet per 16 data packets. And there is a post in this thread where someone says he just started streaming without any start command.

As far as I understood there is a clock that clocks the adc. The adc data lines are read by the fx2 and placed in a buffer somewhere on the FX2 chip (lets say 1024 bytes). When the buffer is filled it will start filling another buffer. During that time you need to get the first buffer over to the host because when the second buffer is full the FX2 will start over with the first one. So if you didn't manage to get the first buffer in time there will be a time discontinuity.

Right now the vendor software is using usb interrupt transfers (my driver also). The openhantek dds-120 port is using bulk transfers. So it might be possible to use something else that is be better.

Anyway I need to do some more testing before I can say anything for sure. Right now I have only been testing with the built in 1kHz square wave and with a perfect timed packet drop things can appear very strange.