SA's: Anritsu MS2711/12E vs R&S FSH3 vs Agilent N9340B: Input wanted

[G0HZU]

Imagine if the image I posted for the FSH4 were 500 kHz span rather than 5 MHz.  See the hump close to the center freq?  Looks similar, doesn't it?

Yes, I suspect they could be selecting a wide loop BW to clean up the phase noise at 10kHz so they can make a nice marketing claim about the phase noise at 10kHz. Also, the wider loop BW will mean the PLL will have a faster retune time. It's probably a better compromise compared to having higher noise close in?

See the attached image from Agilent that shows the phase noise optimising modes in their PXA analyser. I've edited out the less relevant traces but you can see the Wide and Narrow loop responses that it swaps between depending on the SPAN setting on the analyser when in non swept  mode.

You can see that by selecting the wide loop BW mode the phase noise at 10kHz offset is about -133dBc/Hz but the penalty is the huge hump of noise further out at 500-600kHz. It doesn't look quite so significant in the graph because it uses a log frequency scale and the hump appears 'less far out' in frequency terms. But either way, the phase noise has a 12dB peak at about 500kHz and is 20dB worse here compared to the conventional 'narrow' mode.

[Mr Simpleton]

Those plots does not behave the way they should!!!!

With a narrow loop filter you will see the VCO characteristics, but with the wide band loop filter this will reflect the reference oscillator noise, inside the loop filter, but with the 20log(n) where n is the multiplication. The hump is usually what you have when the filter is not optimized for noise i.e. you could have even wider band, having the cross over frequency so wide that the noise hump dissapear.

In the two plots I do not see VCO phase noise beeing similiar outside the filter, hence some weardiness is going on 

[G0HZU]

Those plots does not behave the way they should!!!!

With a narrow loop filter you will see the VCO characteristics, but with the wide band loop filter this will reflect the reference oscillator noise, inside the loop filter, but with the 20log(n) where n is the multiplication. The hump is usually what you have when the filter is not optimized for noise i.e. you could have even wider band, having the cross over frequency so wide that the noise hump dissapear.

In the two plots I do not see VCO phase noise beeing similiar outside the filter, hence some weardiness is going on 

All I do in my plots is to dynamically alter the phase detector gain by changing the register contents in the PLL chip (i.e. it's done in software in the blink of an eye). The hump in the noise will be due to a poor phase margin in the wide mode. I don't have much control over this via software...

I don't actually know what Agilent do with the PXA to get the Wide and Narrow modes but you can see they get similar results with the benefit of the 'close in cleanup'  bu the penalty of the far out 'noise hump' when in wide mode.

[Mr Simpleton]

I bet most modern frequency synths are using quite wide loop filter and use fractional N divisor and/or a DDS for reference. This allows for wide loop filter and low noise multiplication inside the filter bw, plus having fine resolution. Drawback may be spurs...

[Mr Simpleton]

Yup, I see the plots but as you say, have no clue on what magic sauce Agilent is using. The VCO do show a lot less noise when having the narrow loop filter, and if you say the only change is the phase detector gain I'm lost!

[G0HZU]

I don't know what Agilent do but the method I used in my quick and dirty demo is nothing special or new or 'magic'...

If it helps put your mind at rest, when I simulate my PLL I get exactly the same results as my previous demo plots when I change the phase detector current. The noise at 15kHz improves by about 15dB in the wide mode but there is a peaky hump in the noise at about 150kHz offset as the phase margin reduces a lot in the wide mode.

I think what may be confusing you is that the free running phase noise of the VCO is actually fairly similar to the narrow plot. The wide mode is a bit nasty to the VCO at 150kHz and adds extra noise. i.e. the wide mode totally ruins the VCO noise out at 150kHz because of the wide loop BW and the peaking in the noise at 150kHz due to the poor phase margin in the loop. But the benefit is more cleanup down at 15kHz in this mode. If you look at it this way it will make more sense to you.

[Mr Simpleton]

What is the loop filter cutoff frequency? Is the noise hump outisde or inside the "wide loop filter"?
Guess I do not have a clue on what is going on, as I have only seen  these humps with a noisy VCO  and too narrow loop filters.

IF it is the phase detector generating noise, shouldn't this be filtered out by the LPF? Assuming the hump is outside of loop filer...

[videobruce]

One thing that you guys with access to different SA's with preamps can do is see if and how the Attn & preamp is coupled to the reference level setting. IOW's if the ref. level is dropped (higher sensitivity), will it either turn on the attn, and/or turn off the preamp automatically. Is there a manual/auto selection where that could be turned off?

Unfortunately, this seems to be the case now. 

[Mr Simpleton]

My super simple Signal Hound SA44B do have manual control over the preamp, and it seems fully compensated wrt the ref level.

Have to look how the R&S behaves. My HP does not have pre-amp on/off features.

[G0HZU]

What is the loop filter cutoff frequency? Is the noise hump outisde or inside the "wide loop filter"?
Guess I do not have a clue on what is going on, as I have only seen  these humps with a noisy VCO  and too narrow loop filters.

IF it is the phase detector generating noise, shouldn't this be filtered out by the LPF? Assuming the hump is outside of loop filer...

Maybe this isn't the right thread to be discussing loop theory but I think you are missing something. If I increase the PDet CP current then the loop filter will charge/discharge (up and down in in voltage) quicker. So the loop bandwidth will effectively go UP despite the fact I haven't changed any RC component values in the loop filter. But the phase margin will decrease and this causes the humps in the noise. Result: wider loop bandwidth and peaks in the noise. If I overdid the increase in current then the humps would get huge and peaky as the loop slid towards instability

See the attached simulation plots. They agree with my earlier plot quite well. There isn't anything clever happening here... all I did was alter the CP current to get the change in phase noise profile

[Sailor]

Maybe this isn't the right thread to be discussing loop theory...

In fact, I have found this thread extremely interesting. Being a non-RF person, seeing some of the insights into SA datasheets vs 'The Truth' is enlightening.

GOHZU, what is the PLL board that you are using? Is it a demo, still available, etc? Circuit, code, etc?
Now for some uneducated questions/comments...

If I increase the PDet CP current then the loop filter will charge/discharge (up and down in in voltage) quicker.

Ok

So the loop bandwidth will effectively go UP despite the fact I haven't changed any RC component values in the loop filter. But the phase margin will decrease and this causes the humps in the noise. Result: wider loop bandwidth and peaks in the noise.

I don't understand this. Surely the filter bandwidth has not changed? Is it not just that by increasing the gain of the PD it is generating a higher amplitude correction signal (i.e. more 'noise') at frequencies that are closer to the edge of the loop filter? And if that filter has a low damping factor, then that noise gets through, or is even amplified. Is this what you mean by 'effectively go UP' ?

Of course, I could be so far wrong that it may be hard to answer, but please try...

[G0HZU]

I'm afraid I'm not very good at explaining things using just text but I'll have a quick go...

The loop gain in a typical PLL will be very high near dc and it tails off with increasing frequency and eventually falls below zero at some frequency. If you then increase the CP current you increase the gain of the loop over all this range. This means an increase in loop gain at frequencies above and below the special frequency where there is unity gain around the loop.  So if you increase the gain 'here' you actually create a new place where gain around the loop is unity. This will now obviously be at a higher frequency so the loop now has more bandwidth. Simple

I'm making a very significant increase in CP current from less than 0.5mA to over 5mA so it's no surprise that the loop BW has shot up a lot in my demo circuit.  However, the stability of the loop can be compromised when doing this and a 'visual clue' to the degraded phase margin is when you see peaks in the noise on an analyser.

I used an old Analog Devices eval PCB for my demo. It's an ADF4351 board although the loop filter parts have been swapped many times over the years so it isn't a standard board anymore. However, I think the latest values are only slightly different from the default values on the eval board datasheet.

[G0HZU]

Note: The reason I tend to pop up like a bad stain on spectrum analyser threads is because I used to design the RF downconverter stages for wideband ESM receivers used by gov/mil in the 1990s.

These were effectively the same as our modern spectrum analysers like the Rigol 815 and 1030 in that the (tunable across LF to xGHz) downconverter fed to a digital IF using the (then) state of the art ADCs and DSP. Back then the ADC/DSP was the size of a huge rack system and cost an absolute fortune!

It was effectively a race to see how quickly the whole RF spectrum from LF through to many GHz could be captured in DSP for whatever use the customer wanted. The performance had to be very good in terms of linearity, IF capture bandwidth, low spurious and conventional spectrum analysers were too big and heavy and slow and 'narrow' to be used instead of these specialist and very expensive receivers.

I was lucky to have access to the very best spectrum analysers on the planet back in those days as design/eval tools and I had to study and learn their weaknesses. I also had to design the synthesisers used in the receiver as well as designing the signal path and so I was quite savvy about all this stuff back then. However, I don't design this stuff these days as our product base shifted a lot post 911. The last decent receiver/analyser I designed was way back in 2001

[Sailor]

you actually create a new place where gain around the loop is unity.

Ah, ok. But also where invariably the phase margin will be less, hence peakier and noisier?

Another point, to further demonstrate my lack of knowledge in these areas: 
Somewhere (earlier in this thread, I think), I thought there was the suggestion/implication that a lower close-in noise level was being achieved (at the expense of the humps being discussed) by increasing the loop bandwidth. Or, simplistically, that's the way I read it at the time. I always had the idea that lower-BW --> lower noise but slow locking, larger-BW ---> faster locking but more noise. Did I understand wrongly, or is there a way of suppressing close-in noise but still getting a faster lock?

It sounds like you had an interesting career!

[videobruce]

The reason I tend to pop up like a bad stain on spectrum analyser threads is because I used to design the RF downconverter stages

I wish more would "pop up" here as you have. 

I have ruled out the FSH3 from my original list, but have not ruled out it's replacement the FSH4 other than the street price which probably is out of my range. I did look into the Hameg, but kinda ruled that out as I have in the past due to the lack of interest in the US with the what appears to be the very limited availability.
Add to that, it's AC only, The preamp is only 10db (most others are 17-20db), the preamp shuts off automatically above -10dBm & there appears not to have a marker table.
I did notice on the front of the scope, the R&S name with the Hameg name below it.

I also looked at the R&S FSL & the FSC, but other than the spec sheets, there seems to be very little elsewhere on either, just like the Hameg which gives me pause.

One worst thing about shopping for higher end test equipment like this is trying to get a actual bottom line price.  "List" prices aren't even available unless you hunt and/or call for them. Prices for motor vehicles costing as much as many of these higher end machines are commonly available, why does it have to be different here?

[videobruce]

I have updated my 1st post to include the RSH4 (that replaces the '3' version) and the Rigol DSA-1030A. 

[Mr Simpleton]

Ah, ok. But also where invariably the phase margin will be less, hence peakier and noisier?

Another point, to further demonstrate my lack of knowledge in these areas: 
Somewhere (earlier in this thread, I think), I thought there was the suggestion/implication that a lower close-in noise level was being achieved (at the expense of the humps being discussed) by increasing the loop bandwidth. Or, simplistically, that's the way I read it at the time. I always had the idea that lower-BW --> lower noise but slow locking, larger-BW ---> faster locking but more noise. Did I understand wrongly, or is there a way of suppressing close-in noise but still getting a faster lock?

Nevermind the pd current
[simplistic mode]
If you look at your VCO phase noise unlocked, this is what you will get outside of you loop filter cut off frequency
Inside the loop filter cut off the noise will mainly be due to the referency x 20logN where N is the multiplication of the reference to get desired VCO frequency. With a single loop, and a large N you will get lots of noise close to carrier! You may realize the optimal phase noise behavour is a trade off between switching time, reference spur supression and noise.

With the loop closed, the VCO cannot be "corrected" outside the loop bandwith, with a noisy VCO you may get lower noise inside the loop BW (you might even see a hump  ), but if the VCO is really low noise by it self, you may end up with higher noise with-in the loop BW due to multiplication of the reference
[/simplistic mode]

[videobruce]

If we can get away from this discussion of phase noise, how about DANL??
I've seen the video regarding that which was interesting, but I haven't seen the equivalent for DANL and how that affects various measurements.

[KJDS]

If we can get away from this discussion of phase noise, how about DANL??
I've seen the video regarding that which was interesting, but I haven't seen the equivalent for DANL and how that affects various measurements.

The DANL is the fuzzy line at the bottom of the screen. The wanted signals can only be seen when they are large enough to be above the line. The closer they are to the line then the more error the noise will give to their magnitude. The DANL is usually specified in a 1Hz bandwidth. If you are measuring in a 10Hz bandwidth then the noise is 10 x larger so the fuzzy line will be 10dB higher. If a 100Hz bandwidth then 20dB higher and so on.

Where a spectrum analyzer has a pre-amp then the DANL is usually specified with the pre-amp in. Without it then it will be higher and for each 10dB of attenuation switched in then the DANL will be 10dB higher again.

[Sailor]

@Mr Simpleton: OK, thanks for that. I'll have to go away and mull that over...

@videobruce: Sorry mate, I wasn't trying to hijack your thread. But when I see someone who knows 'way more than me about a subject, I like to try and learn something from them.

[Mr Simpleton]

Sorry about obfuscating your thread m8

Oh well, found a R&S ZVL spectrum (and network) analyzer. Smallish and quite portable but only 220 V. And using XP, took ages to boot 

But what I had to try was the internal preamp... this one was manually controlled and did not switch off when adjusting reference level nor, input attenuator. The ref level maxed at 0 dBm using pre-amp on and 20 dBm with it off.
Fast sweep, and not too bad UI, but nothing I would enjoy using, especially with XP running, big step up from the FSH3.

Guess FSL is a close derrivate, optimized for spectrum measurement. Formfactor and layout pretty much identical.

[free_electron]

The fsh3 is a problem child... When the battery deep discharges it takes out the i ternal charging regulator. It fries the power mosfet. That mosfet is a special 6 pin package and discontinued... The pin order is non-standard...

I have already repaired two of those... A third one was unfixable as it burnt too much of the pcb.

Second , the display... Bleeeeh 320x240 pixels...

[videobruce]

Sorry mate, I wasn't trying to hijack your thread.

Never thought you were, just didn't want to go too far off course on just one aspect of the equation. 

When the battery deep discharges it takes out the i ternal charging regulator.

How/why can that happen??
Yes. that display is for sure the deal killer. One would think this was 1994, not 2014. I'd like to see a user review of the new 4.

[G0HZU]

I'll post up some design tradeoffs/equations for DANL vs linearity later but I can't leave the phase noise cleanup debate ending on doubt

Somewhere (earlier in this thread, I think), I thought there was the suggestion/implication that a lower close-in noise level was being achieved (at the expense of the humps being discussed) by increasing the loop bandwidth. Or, simplistically, that's the way I read it at the time. I always had the idea that lower-BW --> lower noise but slow locking, larger-BW ---> faster locking but more noise. Did I understand wrongly, or is there a way of suppressing close-in noise but still getting a faster lock?

You absolutely DO get better phase noise cleanup of the very close in VCO noise (way inside the loop BW)  if you increase the loop bandwidth. I can give you a classic/extreme example... (which hopefully ends the debate once and for all)

My old HP analyser that dates back to the late 1970s has an LO that runs up at 2 to 3.5GHz but the measured close in phase noise down towards the 2GHz end is approx. -112dBc/Hz at a 500Hz offset.  Yes, that's -112dBc/Hz at a few hundred Hz offset from a 2.1GHz LO carrier frequency. This is achieved because the loop bandwidth is very wide. eg it's set at about 100kHz. I think it actually achieves -112dBc/Hz at 300Hz offset but I can't be bothered to go and check this tonight.

If the loop BW were reduced to 1kHz then there is no way the loop can clean up the (noisy) free running VCO noise to get as low as -112dBc/Hz at about a 500Hz offset.
The penalty for this cleanup is that this analyser has relatively high phase noise way out at 100kHz offset. i.e. the phase noise at 100kHz offset is only a few dB better than the phase noise at 500Hz offset.

[Sailor]

GOHZU, thanks for all your input on this.

(which hopefully ends the debate once and for all)

I'm not sure that it was a debate, at least certainly not on my part - I don't know enough about the subject to debate it . My interest is in trying to understand the mechanism by which it happens. My (one and only) textbook on PLLs certainly doesn't discuss it - hell, it barely has a couple of small sections on general noise considerations in the loop. I guess I'd better broaden my reading...