Thank you for summarizing it much better than what I ever could.
As for my "not really ASIC" comment for Rigol ADC I thank Asmi and you for education. I'm not in ASIC business so my use of terminology will not be correct. What I wanted to say is that while Rigol's ADC obviously is ASIC as a type of product because it is custom made IC that was made by company for their specific use, ASICs are usually made for a very specific function: a switching matrix for a high speed interconnect, a complete integrated sound engine for a synthesizer, or something like that.
In this case, Rigol made "just another ADC", a chip for which there is alternative. Of course that assessment is based on my limited knowledge from what Rigol has published. Maybe they did combine ADC and some sort of DSP to linearize response or something like that.. In which case it would be really single use application specific chip for scopes that could not be replaced easily. And would allow them to have simpler BOM and maybe make significant saving in FPGA resources and such...
But from what I see they still have same architecture as before with ADC-FPGA-App processor. So it seems any saving would be just in price of chip. I personally think it is more about control of sourcing the chip than good price (which is just a bonus).
You are welcome!!
The ADC, or FPGA, is likely the single most expensive IC component in the DSO, and at this price point every $ in BOM matters. Without a custom in-house ADC, one is restricted to available chips from AD, TI and maybe some others, and don't think that anyone can get these ADCs at a price that would fit this price point.
We must remember that TI, AD and others have developed and produced high end performing ADC chips that satisfy many market segments, these incurred much higher development costs, and likely occupy more precious silicon area, involve extensive testing and so on. Whereas Rigol was able to isolate the important parameters that are more meaningful to the DSO market, trim the architecture to reduce the up front development costs, reduce the Si area, and so on.
Would wager that if we got ahold of one of these ADCs where we could do detailed isolated standalone chip testing, the overall performance would be mediocre in general compared to TI and AD. Things like no missing codes, monotonicity, differential & integral linearity, ENOB, aging, drift, temp, PSRR, and so on would not compare well with the TI and AD counterparts. Many of these parameters aren't that important in a DSO application, I mean who really cares if the ADC has a stuck lower bit, or non-monotonic around the LSBs, and so on. Now consider using this ADC as feedback in a complex high speed control system, stuck bits and non-monotonic behavior would be a disaster indeed!!
So Rigol likely (again we don't know), made a smart decision to create an ADC specific for DSO application use, with a main parameter of yield and recurring chip cost, so they could penetrate this low cost market. We're confident you won't see them selling these in the Open Market as a High Speed ADC tho.
Even with the targeted DSO application, they still had a difficult task ahead with the ADC design and apparently did an admirable job
Of course all this discussion is just hearsay and speculation on our part, but likely rooted with some substance
BTW the suite of tests you recommended earlier would be welcome by many, ourselves included. Lets hope that some qualified knowledgable folks can perform some of the tests
Best,