Does it mean with the single ADC chip inside the sampling rate 1.25Gs will drop to ~300Ms per channel when using all 4 channels? What would be the impact when hacked to 200MHz BW, for example?
Or the sampling rate is hackable too?
Sampling rate is not hackable (or at least nobody managed to do it so far.. because nobody really has it yet)...
ADC is specified at 1.25GSp/s, it might be that it is hard clocked as such, or maybe even that maybe ADC could but FPGA could not cope with data rate. Until there are thousands of them "in the wild" and some capable people work on it, we wont know.
So far, based at what we know now, even when hacking it I would not "open" BW to more than 100MHz. Even at 100 MHz set, BW is probably more than 100MHz, and then signal does not just die suddenly. It gets progressively weaker.
Problem is that with 8Bits, signal soon drops below ADC resolution and you are all right. With 12 bits, that doesn't happen until higher BW, so you would have more aliasing than similar 8bit scope. In 4ch mode aliasing start at 156,25 MHz.
If they are clever, they decrease BW to 100MHz MAX automatically in 4CH mode...