The cost reduction has to come from somewhere, and there is plenty to reduce in a DS4000 as I stated before (FPGAs, ADCs, memory). I suspect memory and GSPS are not upgradeable, but perhaps decoders and other functions. Obviously we would only be sure after opening one up and comparing IC markings.
Yes we have no idea if any re-design and cost reduction has actually been done.
But let's make a few calculations to see what might be possible with newer generation parts.
We can see in the earlier pictures that the DS4000 has 8 memory ICs per channel group. The part number is H5PS5162GFR which is a 32Mx16 DDR2 SDRAM.
So that is 64 MB per IC. So with 8 ICs total -> 512 MB memory. The spec for the scope is 140 MS so you would be able to fit that data over 3 times in the available memory. Not sure how Rigol is using the memory and if all of it is in use.
Total bandwidth needed to sample at 4 GS/s would be 4 GB/s. As there is 8 SDRAM ICs that is 512 MB/s per IC.
These are 16 bit wide so that would mean minimum 256 MHz memory clock + overhead. Let's say the memory interface would be running at DDR2-533 to have some headroom available. Not sure how fast memory interfaces are possible with Virtex 5.
Ok, googling "virtex 5 ddr2 bandwidth" helps:
http://www.xilinx.com/support/documentation/application_notes/xapp858.pdfSo looks like speed grade -1 Virtex 5 actually supports up to DDR2-533 for that reference design.
I think the current generation low cost FPGA from Xilinx would be Artix 7 probably.
http://www.xilinx.com/products/silicon-devices/fpga/artix-7.htmlThere it is mentioned that these support DDR3-1066 memory interfaces.
That would mean that you would be able to have similar bandwidth with the memory IC quantity reduced to half. That would allow reducing the FPGA I/O amount and package size needed.
That could be one way to reduce cost with newer components.
I don't think reducing the amount of memory would really offer much cost savings though. And if you need 4 memory ICs to get the bandwidth needed and consider the SDRAM IC sizes these days you might end up with quite a lot of memory anyway. So I think the sample memory size specification in a cost reduced design would be more about marketing and positioning the device in the overall product portfolio offered.
It seems the new DS4000E doesn't have much savings in the ADC performance area as if it supports 2 GS/s at the same time on all channels then the ADC capability and memory bandwidth needed would be similar to regular DS4000.
So who knows, maybe the E models are just the same hardware.
And if anyone notices errors in my calculations let me know.