DS1052E and other comparable scopes use 10 interleaved 60msps ADCs overclocked to 100mhz. ETS is accomplished by using a CPLD to generate phase offset clocks in a deterministic way. This is possible since the sampling clocks are a low 100mhz.
DS2k and DS1074 series use higher integrated ADCs.
DS2k uses a National dual channel ADC with internal sample bridging. DS1074Z uses a Hittite quad ADC overclocked that internally bridges for higher rate. Sampling clocks are much faster.
To support ETS with these designs you will need a method of adjusting sampling phase with low jitter (you can't use an FPGA PLL for this).
Instead you need a more specialized RF synthesizer chip, or clock jitter cleaner, each which adds another $15 to the BOM. So there you go. You can't apply the CPLD method since you'd have to drop the sample clock way down, and yoru ETS would drop by a factor of 10, which makes it just the same as your 1gsps real time.