Hi all,
I have been testing (or playing
) with my new DS1054Z lately and found a strange issue, which may have been discussed before in this forum.
The issue is that if i view a full screen waveform (all 8 divisions), and I make a single trig in order to stop the triggering after one trigger. Now, if I zoom in, I don't have a 8 bit resolution (full scale divided by 256), Instead I have just about 160 counts resolution.
Example: full scale signal of 8 divisions, 200mV/division = 1600mV. Now if I zoom, I would expect a step size for the AD conversion at 1600mV/256 = 6.25mV. The problem is that I have a step size of 10mV which is only 1600mV/10mV = 160 counts.
Now, If I make the same signal (1600mV) and turn the vertical vernier so that the signal fills 5 divisions (320mV/divison), the signal of course looks perfect.
Now, with the same signal (1600mV), I half the vernier to 160mV/division so that the signal actually fills 10 divisions (this means that the signal is more far out than the screen borders), and make a single trigger. Now, I go back to 320mV/division, and I can see that I still have my full, undistorted signal.
Now, if I zoom in at the signal captured at 160mV/division (but out of borders, still not destorted), I can see that the I have a step size of 6.25mV, which is exactly 1600mV/256, so now I suddenly have a 8 bit resolution. Hooray.....!!
My conclusion:
Based on this, I calculate that the DS1054Z calculates with 10 divisions vertically internally in the AD conversion algorithm.
If you/I want the best possible resolution, make the signal 5 divisions tall, and hereafter half the vertical vernier and do a single trigger, this will make the best possible vertical resolution.
A full screen signal (as close to 8 divisions as possible) will not (as many people say) give the best resolution. This is instead 5 divisions on the DS1054z
Now, my question;
Why is my Rigol DS1054z calculating with 10 divisions vertically instead of 8, which is how my screen is divided, and I would expect that a full screen is divided into 256 steps (8 bit resolution)?
I don't understand this
Do we have a bug here?
Thank you for your reply
Rigol DS1054z
SW: 00.04.04.SP3
Board: 0.1.4