HP 3325A offset - really puzzled

[LazyJack]

Hi, I'm working on a HP 3325A function gen, and I hit a very puzzling problem.
It has an asymmetrical offset problem. Set it to DC offset. From 0 +5V works perfectly, but anything below zero is wrong. -5 goes to -13.7V (without 50ohm termination, with it, half of it of course). Below about -2,5V just simply saturates the output to the negative side.
So far what I have ruled out: DAC and S&H - OS2 test point goes perfectly from 10 to -10 as it should when setting the offset from one site to the other. OS1 correctly tracks the offset, if A-CAL is done.
Output amplifier is OK, I have measured the current at the AMP-IN test point, and it is perfectly linear over a 4mA range, which according to the SM it should be from 5 to -5 V offset. Output 0 is 1.5mA as it should (1.5mA is the amplifier input bias current, again, according to the SM).
However, from 0-5V the current is ok, over a 2mA range, but on the negative side from 0 to -5V the current increases, it spans about 5mA.
U38b and Q106 replaced for a test, these generate the -2 to +2 mA offset current. Q113 disconnected to see if the amplitude offset causes it, no.
All semiconductors check (with diode testing, so may be parameter problems) in the offset circuit.
Problem still persists. The only one I have not yet tested is Q108 dual transistor in the current mirror, it may be out of tolerance??? Only one dual transistor in my unit, it is an older version, as described on page 7-18 of the SM .
I'm getting a replacement dual transistor simply to test if it makes any difference, although I'm not convinced that it may be the problem. However, practically nothing else is left to explain this.
Any hints of where I I should look?
Thanks.