This is interesting, although I don't feel I am able to understand exactly what is going on. I will look it over one more time and probably have some questions...
Thank you for the setup, hoping to be able to interpret what is going on.
Let's break it down.
First let's understand the signal path. Leading up to the probe test points.
The chain starts with with a Korad KA3005D. I chose this supply, because it has two criteria that are fundamentally misleading. Number one it consistently has an overshoot of about 100mA beyond it's current limit set-point. Number two, despite being a "linear" supply it injects about 50mV of "ripple/noise" into the IBV of the circuit under test. The next point is it's less than ideal regulation. It seems to not be able to handle transient events, with much elegance. We could do a separate review of this specific unit, but I believe others have done so already.
The PSU is routed to the next item through a "purposely dodgy" set of test leads. They are stranded wire, of unknown origin, and are terminated into the PSU with alligator clips. Certainly not an ideal connection.
The other side of the leads are terminated with screw down, banana style terminations. Those are coupled into female banana receptacles of "high quality" (Pomona electric).
The female banana couples to a deans connector, using solid core OFC wire (very high quality test lead/adapter, I built in house).
The next piece of hardware in the chain is a "hobby grade" power measurement device, from "astro flight" (not sure what pcb is being repackaged inside). That piece of hardware shows me the drop in the leads and shows watt hours used. It draws around 50mA of parasitic current. Again I not trying to build the "best possible" front end power, leading to IBV.
From the power meter we again have well made deans to banana pigtail (overkill quality, built in house).
That is where the external power ends and merges into the IBV section of the circuit in test.
The circuit in test is quite complex, and I won't go into lengthy detail, but it's basically a single phase dPOL and controller (based on an atmel MCU, but with high speed acquisition and switching control topology).
The simulation is the programming interface for the dPOL and controller. There is no better simulation available, as it is built specifically for this circuit topology.
In the programming interface I have control over an internal feedback loop/filter on the POL itself, as well as the sequencing signal sent (via 56 bit com signal) directly to the POL.
The output has been optimized for the "best case scenario". Margining is set up, so is tracking and so is ultra tight VR. Our output voltage on the pol is set to 5.5 volts.
The output V sense is coupled back to the digital filter section/feedback loop. So the meters don't load the front end of the pol AT ALL.
We can clearly see that two calibrated and verified meters are reading very close to 5.5 V. One is set with fast integration time, the other is not. That is a point that should not be overlooked.
The test leads are of high quality and free of faults (the main DMM test lead is shielded and properly terminated into 10Gohm).
The scope probes are active FET units and have been fully deskewed, compensated and temperature calibrated. They have also been nulled against a direct ground, to verify that no noise is being injected in the HF ranges. They are 1Mohm 1.8pF with a ratio of 10:1 and a dynamic range of 5v....the dynamic range is matched to scope input rise time quite well.
So that is a pretty ideal test right? There is a trap though....I was hoping someone would spot it, but maybe it's a bit too complex to be obvious.
Pay careful attention to the voltage min max during the switching pulse. I am triggering off of that event on the scope. Have a look at the readings. We are def overshooting 5.5 V, on both the positive and negative edges of the full switching phase.
There is NO bandwidth limiting on the scope front end. If I was to do some sin x/x interpolation, some averaging and employ a 20MHz input filter (AC coupled) we would completely miss this HF overshoot.
So let me explain the trap now. The POL output has 2 4.7uF caps to help it out. Obviously those caps are ballasted and properly used. They are ultra low ESR multilayer ceramic.
The sense loop has been calibrated to respond out to around 10KHz. OOPS!!!! There should be another set of parallel filters on that control loop!!! I posted the response graph earlier in this thread. So essentially there is a physical ringing external to the POL, but coupled into the control loop. That is why we are overshooting our 5.5 v target, during the POL switching step response
I can go into more detail here, as this is obviously a dramatically over-simplified explanation.....but suffice it to say that we wouldn't have caught these problems on the REAL output of the device, if we hadn't employed this "overkill" methodology of measurement.
Is that peak voltage enough to cause an issue in the turn on sequence of a processor? Dunno....that depends on the processor, application and target use. I know that it's an UN-acceptable scenario in my book. We are overshooting 0.05044 V above our target.
My point here isn't to explain WHY this is happening or how to solve it....the point is simply to illustrate that the simulation fell short of predicting the real world response and that real world response would have been missed with tools of lower bandwidth