Good first interpretation.
Looking at my unit, the AD9288 RREFinA and REFinB are tied to REFout (pins 5,7,6), that makes sense as it's the most accurate reference source available.
With those two references fixed, I think that all three programmable values relate to the two AD603s. Checking around the AD603s, Pin 2 (GNEG - negative voltage increases gain) on both channels are linked together and decoupled to ground - these must be connected to a bias network somewhere (I didn't fully trace it out) and so I don't think they are involved in calibrations (there is no common cal setting for both channels).
Pin 1 (GPOS - positive voltage increases gain) of each AD603 is connect to an RC network, which in turn is fed by one half of an SGM8292 dual high voltage rail to rail opamp, on my unit, on the back of the board, near the ARM CPU. These form gain networks which are then driven by PB0.5 and PB0.7 port pins on the CPU. I Suspect that these are controlling the AD603 gain pin levels using PWM (the alternate functions listed on PB0.5 and .7 list ADC but not DAC).
I think this brings us back to the Firmware controlling gain and, zero and offset via those two pins, doing the appropriate compensations in code. Coarse Gain is fairly self-evident. I suspect that Zero Amplitude and Zero Compensation work together, to give both zero, and equal measurements / deflection for equal positive and negative voltages.
That's my best guess anyway.
(My earlier thoughts about Zero Compensation compensating opamp offsets is probably wrong - they would only be relevant at low signal levels (Zero Compensation exists on all ranges) and would be automatically included anyway in the the Zero adjustments provided).
Other interpretations very welcome!
P.S. I noticed in the AD9288 datasheet that a 10 bit pin compatible upgrade is available. That could be fun if we had full control of the Firmware and FPGA code.
Alas...