Older logic analyzer question.

[cyberbarter]

Thanks TK    That's what I needed.   Good link.  It will get me started.

Much thanks

Cyberbarter

[kb5mu]

Followup question on the Model 64683A Interface Module Z80 Service Information manual ... are they also buffering the address and data bus signals? That might matter for timing.

A scan of that manual would be nice to have.

Thanks!
  -Paul

[gslick]

Followup question on the Model 64683A Interface Module Z80 Service Information manual ... are they also buffering the address and data bus signals? That might matter for timing.

A scan of that manual would be nice to have.

Thanks!
  -Paul

All of the Z80 signals are buffered once through a 74LS241, with the exception of /MREQ, /IORQ, and /WR which are buffered one or more times through a 74LS240. The buffer outputs are always enabled.

Once through a 74LS241 Non-inverting Octal Buffer and Line Driver:
PIN 30 A0
PIN 31 A1
PIN 32 A2
PIN 33 A3
PIN 34 A4
PIN 35 A5
PIN 36 A6
PIN 37 A7
PIN 38 A8
PIN 39 A9
PIN 40 A10
PIN  1 A11
PIN  2 A12
PIN  3 A13
PIN  4 A14
PIN  5 A15

PIN 14 D0
PIN 15 D1
PIN 12 D2
PIN  8 D3
PIN  7 D4
PIN  9 D5
PIN 10 D6
PIN 13 D7

PIN 16 /INT     STAT BIT 7 (Not used by inverse assembler)
PIN 17 /NMI     STAT BIT 5 (Not used by inverse assembler)
PIN 18 /HALT    STAT BIT 6 (Not used by inverse assembler)
PIN 23 /BUSACK
PIN 25 /BUSREQ  STAT BIT 4 (Not used by inverse assembler)
PIN 27 /M1      STAT BIT 3
PIN 28 /RFSH    STAT BIT 2, CLOCK L

Once through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 19 /MREQ    CLOCK J

Once through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 20 /IORQ    CLOCK K

Twice through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 20 /IORQ    STAT BIT 1

Three times through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 22 /WR      STAT BIT 0

Four 74LS241 total, one 74LS240 total.

[gotcha]

Hi gslick

I'd be very interested by a schematics (I read this thread but I have a difficulty to transform the text into something that I could build).
Did you by chance scan the manual ?

Thanks !

[gslick]

Hi gslick

I'd be very interested by a schematics (I read this thread but I have a difficulty to transforl the text into something that I could build).
Did you by chance scan the manual ?

Thanks !

I have an original copy of this manual, which includes a schematic of the preprocessor interface:

Model 64683A Interface Module Z80
Service Supplement
HP Part Number 64683-90903

I'll have to get my scanner set up again so I can scan it.

The main thing is that all of the Z80 CPU signals are buffered through either 74LS241 Non-inverting Octal Buffer and Line Drivers, or 74LS240 Inverting Octal Buffer and Line Drivers.

The complication for using the original Z80 Inverse Assembler is that the CPU PIN 22 /WR signal is inverted (routed three times through a 74LS240 Inverting Octal Buffer and Line Driver) when used as STAT Bit 0. If the logic analyzer is attached through flying leads instead of the preprocessor and the /WR signal is not inverted, the original Inverse Assembler will not function correctly.

The original Z80 Inverse Assembler could be modified to work when the /WR signal is not inverted when used for STAT Bit 0. If I have never posted details here on how to do that, I'll have to do that when I make some time to do so.

[gotcha]

FYI, a Z80 preprocessor documentation (64683-90901) and few others have been given here yesterday: https://forum.vcfed.org/index.php?threads/hp-1650-1651-logic-analyzer-disk-images.53427/#post-1317744

They are now stored in bitsavers : http://bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/

It doesn't seem exactly the same as yours since the reference number differs a bit.

[gotcha]

@gslick do you know why /WR is routed 3 times through the 74LS240 ? A single time would have been sufficient to invert the signal.

EDIT: apparently, it's to make sure (through a propagation delay) the right value is sampled by the analyzer.

[gotcha]

The complication for using the original Z80 Inverse Assembler is that the CPU PIN 22 /WR signal is inverted (routed three times through a 74LS240 Inverting Octal Buffer and Line Driver) when used as STAT Bit 0. If the logic analyzer is attached through flying leads instead of the preprocessor and the /WR signal is not inverted, the original Inverse Assembler will not function correctly.

The original Z80 Inverse Assembler could be modified to work when the /WR signal is not inverted when used for STAT Bit 0. If I have never posted details here on how to do that, I'll have to do that when I make some time to do so.

I see 3 things with the preprocessor interface that require a particular attention:

• /WR (STAT0) in indeed inverted by the preprocessor interface and this would require changing the IA 'program'.
  If you can explain how, it would be great
• The clocks used by the analyzer to sample data are also inverted by the interface (J=MREQ and K=IORQ).
  The data sampling must happen at the end of the read/write.
  In the Z80 IA config file, the sampling is then done on clocks falling edge and should be changed to be on rising edge.
  This change is easy to do in the Analyzer once we have loaded the config file
• /WR (STAT0) has 2 extra delays and /IORQ (STAT1) has 1 extra delays.
  I assume that the goal is to sample /WR and /IORQ values just before the triggering sampling clock (the delay is needed because they change almost at the same time as the clocks)
  Knowing that one of the clock (/IORQ) is itself as a value in STAT1, the delay looks mandatory to get the right STAT1 value.
  Without these delays, we may experience errors/noise in the disassembly

Due to item 3, I have the feeling that we can't really invert assemble safely the Z80 with flying probes.
We may need an interface, even if we don't want all functionalities and the complexity of the original interface.

My target now is to make experiments with a single 74LS240 just to invert /WR and delay a bit /WR and /IORQ signals for the STAT sampling.