I don’t think it’s impossible (or extremely hard) to implement for the digital channels only in an FPGA, without waste of memory even. You’d capture non-sparse by default, but once the number of running zeros or ones exceeds the length of two timestamp plus a sentinel value, you instead[1] emit that sentinel value to indicate that sparse capture is happening now, followed by the current timestamp, and then a second timestamp once the value changes again.
That seems like a simple enough state machine. But it’s also more to handle in software and testing, including wrt history mode, data export and so on. So I think it’s probably those second order implementation costs that made R&S not implement it, not concerns about feasibility and memory usage.
EDIT: But I made a lot of assumptions about FPGAs being in the right path here, and how much they do. If ASICs are doing the capture instead, or there are ASICs which require certain memory layouts, then they would need to support that, too.
[1] For a simpler implementation, don't buffer at all before emitting but just switch to sparse mode at some more arbitrary run length. While you can get unlucky and use more memory with that alternative scheme, you'll still save memory for signals that are "sparse enough".