NEW Keysight HD3

[egonotto]

Hello,

I'm afraid there is a mistake in the Magnova data sheet. Example 1 V/div 50 Ohm 20 MHz. The data sheet says 2.19 mVrms and ENOB 11.5 bit.

11.5 * 6.02 dB + 1.76 dB = 70.99 dB = SINAD.

To achieve this, the signal would have to be around 8 Vrms (at 1 V/div). I suspect that Vrms has been confused with Vpp.

Best regards
egonotto

In case you find to have a monkey face (happened to me) after reading the above...
This will help and also this

Hello,

I don't understand what you mean. Do you think my calculation is wrong?

From Walt Kester:
"Signal-to-Noise-and-Distortion (SINAD, or S/(N + D)
is the ratio of the rms signal amplitude to the mean value of the root-sum-square (rss) of all other
spectral components, including harmonics, but excluding dc"

Read the R&S appnote Zucca linked to. You have to compensate for the full range of the ADC (peak-to-peak). So yes, I think your calculation is wrong 

Hello,
It would be easier if you could tell me exactly where I made a mistake.

But okay, I'll take equation 4 from page 5 of the R&S paper.
ENOB = 0.5 log2(SINAD) - 0.5 log2(1.5) - log2(A/V)

Now we take the maximum possible amplitude and get A = V. So log2(A/V) = 0. Further, 0.5 log2(1.5) < 0.5 which we can approximately neglect.
So we have an approximation:
ENOB = 0.5 log2(SINAD)

According to equation 5, SINAD = PS/PN = (2.9 Vrms/ 0.00219 Vrms) * (2.9 Vrms/ 0.00219 Vrms). So we have
ENOB = log2(2.9 Vrms/ 0.00219 Vrms) = log2(1325) < log2(2048) = 11 < 11.5

11.5 bits is the specification in the data sheet and if you do the math with the formula in the R&S paper you get significantly less.

So where did I make a mistake?

Best regards
egonotto

[nctnico]

See the calculation Andre77 showed in the Magnova thread. This one is correct. You need to go from the full dynamic range of the ADC which is 8Vpeak-peak in case of 1V/div. Your error is using the RMS value for full scale ADC range.

[2N3055]

See the calculation Andre77 showed in the Magnova thread. This one is correct. You need to go from the full dynamic range of the ADC which is 8Vpeak-peak in case of 1V/div. Your error is using the RMS value for full scale ADC range.

Andre's calculation is wrong.

SINAD (SNR if we have no distortion) is ratio of RMS full range and RMS noise level.

The IEEE has defined terminology and test methods for analog to digital converters in [1]. This includes the following definition of ENOB:
Equation 4    
ENOB=0.5log₂(SINAD)-0.5log₂(1.5) - 0.5log₂(A/V)

The following definitions apply:
V : full-scale range of the device under test.
A : peak to peak amplitude of the sine wave fitted to the output.
SINAD : signal to noise and distortion ratio.

SINAD is defined as
Equation 5
SINAD = P_S/P_NAD

The following definitions apply:
P_S : signal power; power in the FFT bin corresponding to the input frequency
P_NAD : noise and distortion power; sum of powers in all other frequency bins excluding the 0 frequency bin, up to and including the bin at Nyquist frequency

Here it is noted that SNR and SINAD, as defined in [1], are ratios of ‘rms’ (root mean square) values and not a ratios of power values which is for example typical for communications engineering.


[1] IEEE Standard for Terminology and Test Methods for Analog-to-Digital
Converters, IEEE Standard 1241-2010


*** R&S
The Effective Number of Bits (ENOB) of my R&S Digital Oscilloscope
Technical Paper

[egonotto]

See the calculation Andre77 showed in the Magnova thread. This one is correct. You need to go from the full dynamic range of the ADC which is 8Vpeak-peak in case of 1V/div. Your error is using the RMS value for full scale ADC range.

Hello,

What don't you understand about SINAD = PS/PNAD? The power of the signal is not given by Vpp but by Vrms.

Best regards
egonotto

[Martin72]

If we calculate with the values of the Magnova scope, we should perhaps also discuss the results in the Magnova thread instead of continuing on two tracks as we are doing at the moment.

[Someone]

You say there is no limit, so go ahead and write us a software implementation that does it. Others of us can calculate the computational task and know it is non-trivial and there are limits.

I don't have to, the authors of libraries like OpenGL have already done that. Or do you think upscaling and applying a simple moving average shader is "non-trivial"? There's no requirement that your DSP engine and your display engine share resource constraints!

There are no hard _limits_ to this, just market and product _choices_. Which was my point. That Keysight could have, but chose not to, use a higher-res screen even if the "intensive" calculations happen elsewhere and are simply rendered at screen-res. They could have even kept the hw rendering and have it composited with a nicer UI (straightforward to do on a Zynq with its GPU)

If it really is as simple as using openGL then why won't you show the world how easy it is to break through this barrier? Make some synthetic ADC data and benchmark how quickly you can turn that into a 2d histogram, show us that it doesn't matter what the resolution of the output is (your claim, we dont believe you). You'll become rich if you can replace all these expensive ASICs and FPGAs with some code on an existing embedded GPU.

[nctnico]

See the calculation Andre77 showed in the Magnova thread. This one is correct. You need to go from the full dynamic range of the ADC which is 8Vpeak-peak in case of 1V/div. Your error is using the RMS value for full scale ADC range.

Hello,

What don't you understand about SINAD = PS/PNAD? The power of the signal is not given by Vpp but by Vrms.

I think the method Andre is using isn't correct after all as Wolfgang mentions that the ENOB is unlikely high in the Magnova thread. OTOH I don't think you can use RMS noise floor number and assume a non-existing signal as a reference either.

[EEVblog]

With the front end modules removed, where do the traces up and to the left of J302 go?

That is odd indeed.

[nctnico]

With the front end modules removed, where do the traces up and to the left of J302 go?

That is odd indeed.

The traces look like two traces which need careful shielding but they aren't differential pairs and they aren't length matched. It could indicate I & Q signals which hints to some kind of network analyser feature.

[EEVblog]

With the front end modules removed, where do the traces up and to the left of J302 go?

That is odd indeed.

Oops, the traces go off under the front end PCB into the CH3/4 ADC chip.
So the ADC chip must have at least 3 inputs, or 4 inputs if that's two single ended signals.

[EEVblog]

Shooting my PCB analysis video now and I'm confused.There are only 3 main heatsink chips.
Two that are obviously the new 14bit ADC, two channels each, diff signals in, BUT they are connected direct to the memory chips.
And the top heatsink chip has "FPGA DONE" next to it on the silkscreen which indicates it's an FPGA and not the Megazoom V ASIC.
Are the ADC's actually inside the Megazoom V ASIC? A hybrid chip maybe? 

[EEVblog]

The traces look like two traces which need careful shielding but they aren't differential pairs and they aren't length matched. It could indicate I & Q signals which hints to some kind of network analyser feature.

They do look length matched.

[Anthocyanina]

Shooting my PCB analysis video now and I'm confused.There are only 3 main heatsink chips.
Two that are obviously the new 14bit ADC, two channels each, diff signals in, BUT they are connected direct to the memory chips.
And the top heatsink chip has "FPGA DONE" next to it on the silkscreen which indicates it's an FPGA and not the Megazoom V ASIC.
Are the ADC's actually inside the Megazoom V ASIC? A hybrid chip maybe? 

I think this is unlikely. If the megazoom 5 ASIC is packaged with the ADC that would mean packaging one of those in a lower cost scope is leaving them with one chip less to put in a higher cost scope like the HD3, and allowing for the potential hacking of the lower cost scopes to get the full features of at least the HD3 (minus analog frontend, of course) no? am i not understanding how they'd go about product segmentation?

plus, this would also work against them in the other direction, what about a potential HD4? or would the HD3 and the infiniium EXR together cover the space without a product segment gap?. but if they are planning an HD4 and higher for the infiniivision range, wouldn't having the ADCs baked in with the ASICs mean the HD4 and higher would be just more expensive HD3s?

hmmm, now i wonder if they actually baked the ADC in with the megazoom ASIC and the HD3 is a firmware-crippled version of the full thing 

[mikeselectricstuff]

Or maybe Megazoom is actually implemented in an FPGA

[EEVblog]

Or maybe Megazoom is actually implemented in an FPGA

Nope. Confirmed that the Megazoom V and the new 14bit ASIC share the same chip, a "scope on a chip" as Keysight are calling it 
Still don't know if it's a hybrid or the same silicon process.

And with what looks like 4 ADC inputs per chip, this would be killer for a lower end HD1 or HD1. All you need extra is a Xilinx Zynq and that's it.
Still don't know what the FPGA is, but I assume it's just doing some display integration, as the Megazoom maps data direct to the display, but the processor needs to map som GUI stuff too, the FPGA would combine that.
Processor doesn't do much, they didn't even bother with the heatsink.

[EEVblog]

Teardown video rendering now.

[2N3055]

Or maybe Megazoom is actually implemented in an FPGA

Nope. Confirmed that the Megazoom V and the new 14bit ASIC share the same chip, a "scope on a chip" as Keysight are calling it 
Still don't know if it's a hybrid or the same silicon process.

And with what looks like 4 ADC inputs per chip, this would be killer for a lower end HD1 or HD1. All you need extra is a Xilinx Zynq and that's it.
Still don't know what the FPGA is, but I assume it's just doing some display integration, as the Megazoom maps data direct to the display, but the processor needs to map som GUI stuff too, the FPGA would combine that.
Processor doesn't do much, they didn't even bother with the heatsink.

It is very possible  that ADC ASICs don't have full "scope on chip" like previous generation, but only scope specific parts. And part of MZ implementation sits in FPGA.
That kind of modular approach would really lend itself to making a line of scopes..

[EEVblog]

Nope. Confirmed that the Megazoom V and the new 14bit ASIC share the same chip, a "scope on a chip" as Keysight are calling it 
It is very possible  that ADC ASICs don't have full "scope on chip" like previous generation, but only scope specific parts. And part of MZ implementation sits in FPGA.
That kind of modular approach would really lend itself to making a line of scopes..

There has to be some external FPGA for the display because you have two Megazoom V ASIC trying to dump data into it.
They never had a "scope on a chip before", it was always separate ADC and Megazoom chips.

[nfmax]

I wonder if the MZ5 actually contains an ADC toolkit, that can be reconfigured to trade off between bit depth, number of channels, and sample rate? It could explain the mysterious N-shaped hole that Dave found: as a wider bandwidth RTSA type input. Might be a way of working around the Tek patents on combining time and frequency domain processing channels behind a common acquisition system. This may get interesting!