I dunno if another one of these "inside scoop" presentations is in order, but this one for the Stingray ADC was super cool: https://youtu.be/pdbzIwelCL4?t=99
KS learned a lot (everyone did!!) from the famous Fujitsu 8 Bit 65GSPS Dual ADC in 65nm CMOS developed way back for early Fiber Optic use.
Is this the paper? https://ieeexplore.ieee.org/document/4523224 It's one of the few hits that I can find on search for those keywords (other than tons of people talking about it, lol).
EDIT: nope, this is the trail: https://www.fujitsu.com/cn/en/Images/56G_ADC_FactSheet-en.pdf but I haven't found the paper yet.
The idea that future gains would come from getting good at interleaving was one of the things I took away from the Stingray presentation, so that fits.
It's a bit of a bummer because my R&S scope uses an ADC that went down the other path and while this did wonderful things for ENOB, it has been many years and they have yet to release a followup, so I wonder if they didn't run head first into this wall. Ah well, they've released a few high speed interleaving designs since then, I'm sure they'll get over it. Besides, none of this "cheering for sports teams" is rational to begin with, but ADCs are such wonderful engineering puzzles that I just can't resist the temptation to armchair engineer, lol.
We witnessed the Fugi ADC well before these were published, can't recall the exact date, and soon informed DARPA about it tho.
The ADC started out as 56GSPS then quickly jumped to 65GSPS, had a large array of SAR ADCs with a massive array of small bit number DACs for corrections. This part really set the stage for future high speed ADCs and achieved this performance with 65nm plain CMOS
Would have fun to sit in on the original design concept back when 65nm was a leading technology, probably went something like this:
Designers 1) We want to build a 56GSPS 8 BIT ADC in our new 65nm CMOS for FO use!!
Management 1) We don't have a long history in ADC development, and this is well beyond SOTA!!
Designers 2) That's OK we are Real Smart!!
Managers 2) And how are you proposing to do this??
Designers 3) We'll use hundreds and hundreds of Capacitive Ratioed SAR ADC stages!!
Managers 3) SARs are slow!!
Designers 4) Yep, that's why we'll use hundreds and hundreds!!
Managers 4) Then how are you going to connect them all up??
Designers 5) We'll sample the Inputs with hundreds and hundreds of samplers!!
Managers 5) What about the digital side??
Designers 6) We'll Mux everything with really fast logic!!
Managers 6) Ok, don't you need to match all the individual SARs??
Designers 7) Yep, we'll use large arrays of correction DACs for each SAR ADC!!
Managers 7) So these DACs will correct all the SAR errors and match them, and that's a lot of DACs??
Designers 8~) Yep and we'll get ENOBs around 6 bits or better from all this!!
Managers 8~) Will this correction routine be built-in??
Designers 9) Yep!!
Managers 9) So you think you can do this in 65nm CMOS??
Designers 10) Yep!!
Managers 10) Sounds good!!
Designers 11) BTW we will put two complete 56GSPS ADCs on one chip!!
Managers 11) Well of course!!
Best,
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