Low cost logic analyzer probe for Rigol MSO5000 EasyEDA project

[S. Petrukhin]

Hi, friends!

I'm create project on EasyEDA with circuit and PCB: https://easyeda.com/f33net/digital-probe-rigol-mso5000

This is a low cost logic analyzer probe for oscilloscope Rigol MSO5000 with fixded CMOS/TTL logic for 3.3/5.0V input levels with full bandwidth (up to 600MHz if it realy happens during research). It can also be connected to other models with an adapter or using a different cable.

All components are accessible on LCSC. You can order board and all components for about $20 (plus shipping) in a couple of clicks.

Of course, you will not get beautiful wires with tags for half of the price of an oscilloscope cost for (fuck them) $400!

Thanks to guys from EEVblog for pinout of the connector!

Dear friends, good news!
The Probe is assembled and checked, works correctly.
Checked from the built-in generator at 15MHz (generator limit).

[Gandalf_Sr]

Sorry to be the bringer of bad news but it looks to me like there are issues with your design. 

If you look at my pinout (below) for my (proven and tested) MSO5000 Budget Logic Analyzer Probe Set design, you will see that pin 1 is top right as you look into the MSO5000 connector, if your picture of the PCB is top side up i.e. the logic inputs are on the top side of the PCB, then your pin 1 on the 50 pin connector is going to be top left.  Even if your PCB is plugged upside down, making your pin 1 bottom right, it's still wrong because your pin 1 is now attached to pin 2 (both happen to be ground) but then your pin 2 of D7+ would be connected to the MSO5000's nProbeDetect pin.

It also looks like you have got other pins wrong on the 50 pin connector; your pin D6- has D7- next to it but it should be D7+.

I would also have at least one 0.1 bypass Cap for each driver IC.

Physically, your 50 pin connector isn't going to fit.  There can't be any PCB around it as it fits into a shrouded (surrounded) receptacle so your PCB area under the connector is not going to work and PCB either side of the connector also isn't going to work.  This is why I set mine up so that a non-right angle connector puts pins either side of my PCB; my thread includes pictures of this.

You seem not to have any input protection at all for your LVDS driver ICs, the data sheet says the absolute max input voltage is 5V so logic that hits 5.2V may cause problems.  I would have fed these inputs via 200  series resistors.

Assuming you fixed the problems with the 50 pin connector, your design will only work at 3.3V and 5V levels.

Also, the 50 pin connector has to be a socket, not a plug. Mine is this one.

[ebclr]

I like the idea to use a one channels IC ( SN65LVD....)  , Then I think, what about Put this IC  on the other side of the cable just on the tip, and use 4 wire for each channel ( +Vcc GND D+ D- ), On the mainboard will make only a motherboard to connect the cable of the tips boards with some termination if necessary, I believe will have a much better spec because wee will have a differential transmission line.

[Gandalf_Sr]

I like the idea to use a one channels IC ( SN65LVD....)  , Then I think, what about Put this IC  on the other side of the cable just on the tip, and use 4 wire for each channel ( +Vcc GND D+ D- ), On the mainboard will make only a motherboard to connect the cable of the tips boards with some termination if necessary, I believe will have a much better spec because wee will have a differential transmission line.

Other than the one-IC-per-channel, that's the approach some guy called Gandalf_Sr (aka moi) took with his design.

First he used a voltage level translator to allow a range of logic input voltages and then, as close as possible to the point of capture, he changed the signals to LVDS.  He then fed the LVDS signals up the ribbon cable as a differential transmission line, and then tried (as far as possible) to make the Connector PCB routing correct for differential pair and impedance purposes.

The 3.3V version has been tested at 200 MHz, the limit of the MSO5000 input.

I know that he still has some spare PCBs if you want a set.

[S. Petrukhin]

Sorry to be the bringer of bad news but it looks to me like there are issues with your design. 

If you look at my pinout (below) for my (proven and tested) MSO5000 Budget Logic Analyzer Probe Set design, you will see that pin 1 is top right as you look into the MSO5000 connector, if your picture of the PCB is top side up i.e. the logic inputs are on the top side of the PCB, then your pin 1 on the 50 pin connector is going to be top left.  Even if your PCB is plugged upside down, making your pin 1 bottom right, it's still wrong because your pin 1 is now attached to pin 2 (both happen to be ground) but then your pin 2 of D7+ would be connected to the MSO5000's nProbeDetect pin.

It also looks like you have got other pins wrong on the 50 pin connector; your pin D6- has D7- next to it but it should be D7+.

I would also have at least one 0.1 bypass Cap for each driver IC.

Physically, your 50 pin connector isn't going to fit.  There can't be any PCB around it as it fits into a shrouded (surrounded) receptacle so your PCB area under the connector is not going to work and PCB either side of the connector also isn't going to work.  This is why I set mine up so that a non-right angle connector puts pins either side of my PCB; my thread includes pictures of this.

You seem not to have any input protection at all for your LVDS driver ICs, the data sheet says the absolute max input voltage is 5V so logic that hits 5.2V may cause problems.  I would have fed these inputs via 200  series resistors.

Assuming you fixed the problems with the 50 pin connector, your design will only work at 3.3V and 5V levels.

Also, the 50 pin connector has to be a socket, not a plug. Mine is this one.

Hi, Gandalf_Sr!

Sir, thank you very much for your participation and help!

I planned to use a mirror cable:
.
A regular cable 1:1 is convenient when the devices are standing on each other, but it is very inconvenient when they are opposite - you need to twist the flat cable, and this is very inconvenient. So i changed the pins mirrored.

But you are quite right: i turned over the pins, but i did not turn over the rows. This is a mistake, I will fix it.

But different polarities of lines in the same row - this is news to me. Are you sure that the positive and negative inputs are mixed? I could not check it, i found a pinout here in the forum and there is a negative polarity on all lines on one side, and a positive completely on the other. Maybe this was later discussed and fixed, i grabbed the wrong option? Or is Rigol such that its polarity doesn't matter?

Bypass capacitors for each IC, it seemed unnecessary to me. These chips consume very little current, their noise into power line is very insignificant. Do you think that one capacitor for 4 chips is not enough?

Input protection? Yes, i know that the 5V signal can ringing, but the input of these chips is tolerant to 5V, therefore, it is ready to absorb any ringing. Other excess voltages should not be in the circuit under test. At least in the part where you need to pick up the 5V signal. I generally only work with 3.3V logic. I vote for a direct rail-to-rail connection. But, still, in the new version, I will add 100om resistors - those who do not like them will be able to simply short them.

Yes, i designed this device specifically for CMOS/TTL, when you need to take a lot of signals inside the circuit and check, for example, time shifts. For other levels, you can use analog inputs to inspect data on transmission lines. Isn't it?

Thank you again for participating, for a detailed explanation.
I will be very happy if you give your opinion on this message.
And sorry for my English.

[S. Petrukhin]

I like the idea to use a one channels IC ( SN65LVD....)  , Then I think, what about Put this IC  on the other side of the cable just on the tip, and use 4 wire for each channel ( +Vcc GND D+ D- ), On the mainboard will make only a motherboard to connect the cable of the tips boards with some termination if necessary, I believe will have a much better spec because wee will have a differential transmission line.

Hi, ebclr!

Yes, these chips are tiny and can be placed directly in the test clip body, connect each 4 wires. It's convenient, i agree. But then each test clip should get its own GND tail and this is inconvenient. It is not possible to take one GND from the board for all because you will get a loop on the GND. I think it will be bad.

[Gandalf_Sr]

The mirror cable solves part of my concern. What I can tell you is that the pinout for the MSO5000 connector that I posted above is tested and correct.

[S. Petrukhin]

Quote from: Gandalf_Sr on Yesterday at 23:49:38

The mirror cable solves part of my concern. What I can tell you is that the pinout for the MSO5000 connector that I posted above is tested and correct

.

I lost the message where I found pinout. A lot of messages in the topic. You followed and participated in the discussion. How did you find pinot?

[Gandalf_Sr]

Quote from: Gandalf_Sr on Yesterday at 23:49:38

The mirror cable solves part of my concern. What I can tell you is that the pinout for the MSO5000 connector that I posted above is tested and correct

.

I lost the message where I found pinout. A lot of messages in the topic. You followed and participated in the discussion. How did you find pinot?

I got the pinout from this thread https://www.eevblog.com/forum/testgear/rpl1116-active-logic-probe-pod-for-1000z-series-teardown/

There was an early version in that thread that had some of the + & - LVDS pins swapped but I promise you mine above is correct.

[S. Petrukhin]

Quote from: Gandalf_Sr on Yesterday at 23:49:38

The mirror cable solves part of my concern. What I can tell you is that the pinout for the MSO5000 connector that I posted above is tested and correct

.

I lost the message where I found pinout. A lot of messages in the topic. You followed and participated in the discussion. How did you find pinot?

I got the pinout from this thread https://www.eevblog.com/forum/testgear/rpl1116-active-logic-probe-pod-for-1000z-series-teardown/

There was an early version in that thread that had some of the + & - LVDS pins swapped but I promise you mine above is correct.

Thank you very much, sir!

I get pinout from message number 3 at the beginning of the thread. But I looked at the topic more carefully, saw a photo of the original board, where we can see clearly the different polarity of the pins of some channels. Later in the discussion, people talked about the reverse polarity of some channels on the scope screen. And then the correct pinout appeared. You even asked about it. Well, I lost 10 bucks and will throw out the PCB that is already in delivery or solder the cable without a connector, taking into account the permutations.

Thank you very much!

[S. Petrukhin]

Chinese comrades are having a blast...   
However, I lived in the USSR and understand a little how the system works... 

[nctnico]

I strongly recommend to design for the regular cable and not use tricks like mirroring.  It will get messy at some point. You can mount the connectors on different sides of the flat cable without changing the order of the pins to achieve the same.

[S. Petrukhin]

I strongly recommend to design for the regular cable and not use tricks like mirroring.  It will get messy at some point. You can mount the connectors on different sides of the flat cable without changing the order of the pins to achieve the same.

OK, I'll change the angle connector to the regular and make the design for the regular cable.
Using a angle connector with a regular cable is very inconvenient.

Give me a few hours for a new design.

[S. Petrukhin]

OK, friends!

The new design is complete.
It is in the same project as version 2.0.

Thank you all for your help and participation.

[nctnico]

I took a look at your schematics. Why are there 100 Ohm resistors between the LVDS signals at the driver side? These shouldn't be there. LVDS is terminated at the receiver. LVDS is a current sourcing/sinking signaling system and adding extra load is reducing the swing at the receiver.

[S. Petrukhin]

I took a look at your schematics. Why are there 100 Ohm resistors between the LVDS signals at the driver side? These shouldn't be there. LVDS is terminated at the receiver. LVDS is a current sourcing/sinking signaling system and adding extra load is reducing the swing at the receiver.

I'm not sure exactly about LVDS, but the terminating resistor is placed on both sides of a symmetrical line, isn't it?
Correct me if I'm wrong.
In any case, you can not install these resistors at will.

[ebclr]

Your English is just fine, Don't worry about

[Gandalf_Sr]

I took a look at your schematics. Why are there 100 Ohm resistors between the LVDS signals at the driver side? These shouldn't be there. LVDS is terminated at the receiver. LVDS is a current sourcing/sinking signaling system and adding extra load is reducing the swing at the receiver.

I asked about this here.  The answer was that the guts of the MSO5000 don't appear to have any terminating resistors - I think the internal IC inputs are RSPECL.  So you have to terminate the LVDS signals (which are current signals) on a 100 or 120 Ohm resistor to convert them to voltages.  Keep reading from my link and you'll see a load of discussion on that page.

In some respects I was designing a circuit with an output into an unknown input although there are some good breakdown photos. Anyway, I have these LVDS terminating resistors on my design and it works with them and it doesn't work without them.

Long story short, I think Sergey is right to include the terminating resistors.

[S. Petrukhin]

I took a look at your schematics. Why are there 100 Ohm resistors between the LVDS signals at the driver side? These shouldn't be there. LVDS is terminated at the receiver. LVDS is a current sourcing/sinking signaling system and adding extra load is reducing the swing at the receiver.

I asked about this here.  The answer was that the guts of the MSO5000 don't appear to have any terminating resistors - I think the internal IC inputs are RSPECL.  So you have to terminate the LVDS signals (which are current signals) on a 100 or 120 Ohm resistor to convert them to voltages.  Keep reading from my link and you'll see a load of discussion on that page.

In some respects I was designing a circuit with an output into an unknown input although there are some good breakdown photos. Anyway, I have these LVDS terminating resistors on my design and it works with them and it doesn't work without them.

Long story short, I think Sergey is right to include the terminating resistors.

Yes, I also looked at the photo - there the connector pins are connected to an array of resistors on the visible layer. There may be tracks on the inner layer for terminating resistors, but you can't see the tracks and resistors. And I looked at how it is done on your disign. 

But why do you say it's a current line? Maybe I not understand the terminology in English, but this is not a line like 4..20 mA, where the signal is transmitted by current. Aren't these resistors the matching ones for the wave resistance?

[Gandalf_Sr]

...But why do you say it's a current line? Maybe I not understand the terminology in English, but this is not a line like 4..20 mA, where the signal is transmitted by current. Aren't these resistors the matching ones for the wave resistance?

If you look at the first picture at this link on LVDS, you will see that LVDS, at its heart, is a 3.5 mA constant current supply that is switched via an 'H' bridge circuit so it actually, it IS a current system which is why you need the terminating resistor to get you the the Hi and Lo voltage levels that the RSPECL inputs expect.

[S. Petrukhin]

...But why do you say it's a current line? Maybe I not understand the terminology in English, but this is not a line like 4..20 mA, where the signal is transmitted by current. Aren't these resistors the matching ones for the wave resistance?

If you look at the first picture at this link on LVDS, you will see that LVDS, at its heart, is a 3.5 mA constant current supply that is switched via an 'H' bridge circuit so it actually, it IS a current system which is why you need the terminating resistor to get you the the Hi and Lo voltage levels that the RSPECL inputs expect.

Understood. Thanks! 

[tv84]

Anyway, I have these LVDS terminating resistors on my design and it works with them and it doesn't work without them.

Long story short, I think Sergey is right to include the terminating resistors.

Nothing beats the experimental method.   

[sbehnke]

Looking forward to your testing to see if this works as designed. I'd love to order one for myself.

[S. Petrukhin]

Looking forward to your testing to see if this works as designed. I'd love to order one for myself.

Unfortunately, delivery is very slow now, I'm still waiting for LVDS drivers. Subscribe to this topic - I will definitely inform here.

[S. Petrukhin]

Dear friends, good news!
The Probe is assembled and checked, works correctly.
Checked from the built-in generator at 15MHz (generator limit).

D0-D7 inputs are connectet to first built-in generator at 5MHz.
D8-D15 inputs are connected to second buid-in generator at 15MHz (generator limit).
CH4  input is connected as D8-D15 inputs.
Both generators have settings: Square, MinLevel=0V, MaxLevel=2.5V (generator limit).
Trigger from CH4.