ethrent connection to hp 1670e logic analyzer

[TK]

STAT information for 6502 (From 6502.S source file)

* Inverse assembler for the Western Design Center W65C02S
*
* INPUT_STATUS bits:
*             _
*   7       R/W
*           ___
*   6       RST
*           ___
*   5       NMI
*           ___
*   4       INT
*
*   3       SYNC
*
* Logic states must be clocked in on the falling edge of the 6502's
* PHI2o (phase-2-out) clock.

[gslick]

STAT information for 6502 (From 6502.S source file)

* Inverse assembler for the Western Design Center W65C02S
*
* INPUT_STATUS bits:
*             _
*   7       R/W
*           ___
*   6       RST
*           ___
*   5       NMI
*           ___
*   4       INT
*
*   3       SYNC
*
* Logic states must be clocked in on the falling edge of the 6502's
* PHI2o (phase-2-out) clock.

OK, I finally found a link to a ia6502.zip file which appears to contain the same 6502.S IA source file.  Looking at the source code it is clear that the SYNC signal is the LSB of the STAT label, and R/W is the MSB of the STAT label.

What I am missing is what does the 3 - 7 mean for the STAT signals in that above comment? The bit positions in the STAT label would be 0 - 4?

Code: [Select]

NOT_TAGGED
* what state is the CPU in?
    LOAD        INPUT_STATUS
    IF          0,0 = 1 THEN GOTO DECODE_OPCODE          ; opcode fetch

    CASE_OF     4,1
        OUTPUT  RESET                ; 0000  RESET
        OUTPUT  RESET                ; 0001  RESET
        OUTPUT  RESET                ; 0010  RESET
        OUTPUT  RESET                ; 0011  RESET
        OUTPUT  UNKNOWN              ; 0100  NMI AND INT (ILLEGAL)
        OUTPUT  NONMASKABLE          ; 0101  NMI
        OUTPUT  INTERRUPT            ; 0110  INT
        OUTPUT  MEM_WRITE            ; 0111  MEM WRITE
        OUTPUT  RESET                ; 1000  RESET
        OUTPUT  RESET                ; 1001  RESET
        OUTPUT  RESET                ; 1010  RESET
        OUTPUT  RESET                ; 1011  RESET
        OUTPUT  UNKNOWN              ; 1100  NMI AND INT (ILLEGAL)
        OUTPUT  NONMASKABLE          ; 1101  NMI
        OUTPUT  INTERRUPT            ; 1110  INT
        OUTPUT  MEM_READ             ; 1111  MEM READ
    CASE_END

    RETURN                           ; not an op fetch so exit

[TK]

I agree STAT signals should be 0-4, 0 being SYNC.  Probably 3-7 was left in the source file as a comment and never updated.

[Dan Moos]

What about the clock?
 
It says (as I would expect) that I should clock on the falling edge of ph2o. But when I load the IA, it sets itself up to clock on the falling edges of the J+K clock. Is "+" an OR symbol, or and and? Also, what would I hook up to the second clock?

It seems like things aren't exactly synced as they should be for me. I have it set to trigger on an address where a bit of code starts. It interprets that first opcode correctly. It seems to interpret most things correctly, but sometimes, it seems like it isn't taking the number of cycles an instruction takes into account properly.

i initially had the STAT label bits set as the .txt file instructed (3-7). I now have it 0-4, in the order the file suggested, with SYNC being the LSB. I don't think it really made a difference.  It definitely seems to be getting the R/W line right. I haven't tried to throw it an interrupt yet, but I'll try that next.

Here is a perfect example of what is happening:

My code says:

 STZ $05

that opcode should take two bytes, and three cycles.

The interpretation by the IE is: (status bits from left to right are R/W, RST, NMI, IRQ, SYNC)

3  80F7   64    STZ  $81           11111
4  80F7   64    STZ    $80           11111
5  80F9   05    memory read     11110
6  0005   00                            01110 

to me, line 4 is shouldn't exist, which could be why line 3 is wrong (should be STZ $05)

if you took away line 4, it wouldn't be off the rails to me. It feels like a clocking problem.

This result is completely repeatable, so its not noise on the clock line.

[Dan Moos]

I'm also not clear on how to properly load the IE.

I seem to be able to load either the I6502 or the C6502 files as analyzers. They seem to do he same thing, although C6502 is a way bigger file. Also, I'm not sure what happens when I load them one after the other as an analyzer. I know the .S file is the source. Not sure what to do with the .R file. I had thought before now that it was what I was supposed to load.

I guess my questions are, what files do I load, and what do I load them as?

[gslick]

Where did you get the files you are using? I found a link to an ia6502.zip file here:
https://stardot.org.uk/forums/viewtopic.php?t=11043

That ia6502.zip file contains:
 2,690 6502.A
    14 6502.BAT
 9,452 6502.R
27,480 6502.S

The 6502.S file is the IA source file. The 6502.R file is the relocatable output binary file that is produced by the 10391B assembler when it processes the 6502.S the IA source file. The 6502.R relocatable file is processed by the logic analyzer when the file is downloaded to the analyzer and transformed slightly into the IA file as it is stored on the analyzer disk. The 6502.R relocatable file cannot be loaded directly on the analyzer without going through the download transformation.

(I forget exactly what the 6502.A file is, possibly a temporary symbol file used by the 10391B assembler when it processes the 6502.S the IA source file, which has no real use when the processing is complete).

The ia6502.zip file I found does not contain a C6502 configuration file, or a downloaded version of the 6502.R relocatable file.

An IA file contains instructions (and any necessary constants, variables, and strings) that are interpreted by the analyzer to decode each state in a state listing. It doesn't contain any information on how to set up the analyzer.

A configuration file contains all of the information necessary to set up the analyzer. Timing mode vs. state mode, what pods are assigned to each analyzer, what channels are assigned to each label, channel polarity, pod mode (master, slave, demultiplex) clock configuration (which clock(s), polarity, qualifiers), trigger configuration, symbol definitions, etc. It can all add up to a large amount of data. A configuration file can also specify an IA file to be loaded, so if you load a configuration file which specifies an IA file, they both get loaded together.

[Dan Moos]

Do I load these files as analyzers? You have to choose between All, system, analyzer, and symbol table. Analyzer seems to work.

I guess, with the files I have, what specificly should I do to load things properly?
 

[gslick]

Where did you get the files you are using? It would make it easier to understand what you are seeing if I could start with the same files.

[Dan Moos]

Here is the link to the ie.:

https://www.eevblog.com/forum/testgear/hp-1631d-logic-analyzer/?action=dlattach;attach=317125

[gslick]

Here is the link to the ie.:

https://www.eevblog.com/forum/testgear/hp-1631d-logic-analyzer/?action=dlattach;attach=317125

Thanks. My searching wasn't working earlier when I only found ia6502.zip somewhere else online and didn't find the 6502_ia.zip file in the thread below.

https://www.eevblog.com/forum/testgear/hp-1631d-logic-analyzer/#msg1213513

That's embarrassing because not only did I post messages in that thread, I also downloaded the 6502_ia.zip file in that thread back in May 2017 when it was posted and I forgot about it and just found on my hard drive the copy I already downloaded.

I'll try loading the 6502 IA file on my 1670E and attach it to a target system and see how it goes for me.

[Dan Moos]

Thanks for your help! I did have dinner better results by grounding my clock probe. I mostly just want to stop guessing on how to make this thing work, and be confident knowing I'm doing it right. I don't really know what things should look like exactly when all is correct. My hope is that every instruction is decoded properly, and that every cycle in between at least make sense.

[gslick]

I finally got around to setting up my 1670E connected to a target 6502 system.

Instead of loading the configuration file from the 6502_ia.zip file I just created a configuration program file from scratch and used FTP to put that program file to the analyzer. This program file assumes that the IA file named I6502 is stored in the directory named \6502 on the analyzer hard disk. If you try using this program file yourself, edit the IA file name and directory name as appropriate for your analyzer.

The inverse assembled states in the list display I captured look reasonable to me. In the capture below the first line in the list begins with the fetch of the reset vector.

Code: [Select]

C:\IA6502>ftp 192.168.1.200
Connected to 192.168.1.200.
220  HP167XE V02.02 FUSION FTP server (Version 3.3) ready.
500 Command not understood.
User (192.168.1.200:(none)): control
230 User CONTROL logged in.
ftp> dir
200 PORT command ok.
150 Opening data connection for  (192.168.1.103,51980).
dr-xr-xr-x    2    1    1       766  status
dr-xr-xr-x    4    1    1       894  system
dr-xr-xr-x    3    1    1       766  slot_a
226 Transfer complete.
ftp: 138 bytes received in 0.02Seconds 7.67Kbytes/sec.
ftp> cd system
200 Remote Directory changed to "/system".
ftp> dir
200 PORT command ok.
150 Opening data connection for  (192.168.1.103,51981).
dr-xr-xr-x    4    1    1       638  disk
dr-xr-xr-x    2    1    1       894  graphics
-rw-rw-rw-    1    1    1      1592  program
-rw-rw-rw-    1    1    1         1  setup.raw
226 Transfer complete.
ftp: 187 bytes received in 0.02Seconds 7.79Kbytes/sec.
ftp> put program
200 PORT command ok.
150 Opening data connection for program (192.168.1.103,51982).
226 Transfer complete.
ftp: 1629 bytes sent in 0.01Seconds 108.60Kbytes/sec.
ftp> bye
221 Goodbye.

Code: [Select]

:SELECT 1
:MACHINE1:NAME '6502'
:MACHINE1:ASSIGN 1,2
:MACHINE1:TYPE STATE
:MACHINE2:ASSIGN NONE
:MACHINE2:TYPE OFF
:MACHINE1:SFORMAT:MASTER J, FALLING
:MACHINE1:SFORMAT:REMOVE ALL
:MACHINE1:SFORMAT:LABEL 'ADDR', POSITIVE, #H0, #H0000, #HFFFF
:MACHINE1:SFORMAT:LABEL 'DATA', POSITIVE, #H0, #H00FF, #H0000
:MACHINE1:SFORMAT:LABEL 'STAT', POSITIVE, #H0, #H1F00, #H0000
:MACHINE1:SFORMAT:LABEL 'SYNC', POSITIVE, #H0, #H0100, #H0000
:MACHINE1:SFORMAT:LABEL '-IRQ', POSITIVE, #H0, #H0200, #H0000
:MACHINE1:SFORMAT:LABEL '-NMI', POSITIVE, #H0, #H0400, #H0000
:MACHINE1:SFORMAT:LABEL '-RST', POSITIVE, #H0, #H0800, #H0000
:MACHINE1:SFORMAT:LABEL 'R/-W', POSITIVE, #H0, #H1000, #H0000
:MMEMORY:CD '\6502', INTERNAL0
:MMEMORY:LOAD:IASSEMBLER 'I6502', INTERNAL0, 1, 1
:MMEMORY:CD '\', INTERNAL0
:MACHINE1:SYMBOL:REMOVE
:MACHINE1:SYMBOL:WIDTH 'STAT', 12
:MACHINE1:SYMBOL:BASE  'STAT', BINARY
:MACHINE1:SYMBOL:PATTERN 'STAT', 'RESET',           '#BX0XXX'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'NON-MASK INT',    '#BX101X'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'INTERRUPT',       '#BX110X'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'MEM WRITE',       '#B01110'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'MEM READ',        '#B11110'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'OPCODE FETCH',    '#B11111'
:MACHINE1:STRIGGER:CLEAR ALL
:MACHINE1:SLIST:REMOVE
:MACHINE1:SLIST:COLUMN 1, 'ADDR', HEXADECIMAL
:MACHINE1:SLIST:COLUMN 2, 'DATA', IASSEMBLER
:MACHINE1:SLIST:COLUMN 3, 'STAT', SYMBOL
:MACHINE1:SWAVEFORM:REMOVE
:MACHINE1:SWAVEFORM:INSERT 'ADDR', OVERLAY
:MACHINE1:SWAVEFORM:INSERT 'DATA', OVERLAY
:MACHINE1:SWAVEFORM:INSERT 'STAT', OVERLAY

[Dan Moos]

First of, that KIM is awesome!

Questions:

I've never read a configuration file, but it seems pretty obvious what it's doing.

I'm curious. You made individual labels for STAT lines, along with single lable that has them all. I presume the individual labels are a convenience, and that the group label is what the IA is looking at?

Next: Your list view on the analyzer is doing something mine isn't. As it happens, your opening assembly code is identical to mine. Not surprising, since setting the stack pointer to FF is the usual first task.

Anyway, when the LDX opcode appears on the data bus, with all ones on the STAT lines, your STAT symbol says OPCODE FETCH. Makes sense. On the next cycle though, your   sync line must go low, because you now show a read, whereas on mine, sync is still high. I assume that KIM has an original NMOS 6502, whereas my homebrew has a modern CMOS 6502. Perhaps it handles sync differently?

Finally, is it standard that the configuration file should load the IA?

[TK]

That is a very impressive 8-bit vintage setup!!

[Dan Moos]

UPDATE:


Things seem to be working as they should now. I noticed that when I probed SYNC with my oscilloscope, SYNC started appearing correctly on th analyzer. I put some capacitance from that pin to ground (figuring that's what my scope probe did), and voila!

The whole shebang is currently bread boarded, so signal integrity is not great. Just trying to get a few things sorted out before I commit to having a PCB made. It's a 6502 computer, with a 7400 logic only implementation of VGA.  Compared to your typical blinks light project, its gonna be a largish, 4 layer, expensive (to me anyway) board, so I'm trying to breadboard as much as I can before I spend the dough. Its pretty much ready to go, so I'll be off the janky bread board setup soon!

[gslick]

Good to hear that you got things working.

If in doubt when things don't look right in state mode, switching to timing mode instead of state mode to see what the signals are doing all of the time and not just when they are sampled at a clock edge can give you a better picture of what is going on, and if things are really behaving as expected. Then if things don't look right in timing mode, pull out the scope to take an even better look, as you did.

Before I saw your last reply I captured some notes about using timing mode. I added a Phase 1 label in addition to the Phase 2 label that was being used as the state clock so that the relationship of the two clock phases could be observed along with the rest of the signals.

The timing mode waveforms captured below start at the rising edge of the /RESET signal and should match the states listings I posted previously. The first waveform display starts right at the rising edge of the /RESET signal, the second waveform display is scrolled slightly later in time to the right when the first few instructions start executing.

Take a look at the Programmer’s Guide. It's fairly straight forward to figure out the configuration commands. Once you get the hang of it it can be easier to set things up exactly the way you want with a configuration command script instead of trying to use the analyzer front panel keys.

HP 1670E-Series Logic Analyzers Programmer’s Guide
Publication number 01670-97008
First edition, August 1998
https://literature.cdn.keysight.com/litweb/pdf/01670-97008.pdf

Example timing mode configuration command script used for the screen captures below:

Code: [Select]

:SELECT 1
:MACHINE1:NAME '6502'
:MACHINE1:ASSIGN 1,2
:MACHINE1:TYPE TIMING
:MACHINE2:ASSIGN NONE
:MACHINE2:TYPE OFF
:MACHINE1:TFORMAT:REMOVE ALL
:MACHINE1:TFORMAT:LABEL 'PH2',  POSITIVE, #H1, #H0000, #H0000
:MACHINE1:TFORMAT:LABEL 'PH1',  POSITIVE, #H2, #H0000, #H0000
:MACHINE1:TFORMAT:LABEL 'ADDR', POSITIVE, #H0, #H0000, #HFFFF
:MACHINE1:TFORMAT:LABEL 'DATA', POSITIVE, #H0, #H00FF, #H0000
:MACHINE1:TFORMAT:LABEL 'STAT', POSITIVE, #H0, #H1F00, #H0000
:MACHINE1:TFORMAT:LABEL 'SYNC', POSITIVE, #H0, #H0100, #H0000
:MACHINE1:TFORMAT:LABEL '-IRQ', POSITIVE, #H0, #H0200, #H0000
:MACHINE1:TFORMAT:LABEL '-NMI', POSITIVE, #H0, #H0400, #H0000
:MACHINE1:TFORMAT:LABEL '-RST', POSITIVE, #H0, #H0800, #H0000
:MACHINE1:TFORMAT:LABEL 'R/-W', POSITIVE, #H0, #H1000, #H0000
:MACHINE1:TWAVEFORM:REMOVE
:MACHINE1:TWAVEFORM:RANGE 10E-6
:MACHINE1:TWAVEFORM:DELAY 4600E-9
:MACHINE1:TWAVEFORM:INSERT '-RST'
:MACHINE1:TWAVEFORM:INSERT 'PH1'
:MACHINE1:TWAVEFORM:INSERT 'PH2'
:MACHINE1:TWAVEFORM:INSERT 'SYNC'
:MACHINE1:TWAVEFORM:INSERT 'R/-W'
:MACHINE1:TWAVEFORM:INSERT 'ADDR', OVERLAY
:MACHINE1:TWAVEFORM:INSERT 'DATA', OVERLAY
:MACHINE1:TTRIGGER:CLEAR ALL
:MACHINE1:TTRIGGER:ACQUISITION MANUAL
:MACHINE1:TTRIGGER:TPOSITION POSTSTORE, 90
:MACHINE1:TTRIGGER:SPERIOD 8E-9
:MACHINE1:TTRIGGER:EDGE1 '-RST', 'R'
:MACHINE1:TTRIGGER:FIND1 'EDGE1', OCCURRENCE, 1


[gslick]

I'm curious. You made individual labels for STAT lines, along with single lable that has them all. I presume the individual labels are a convenience, and that the group label is what the IA is looking at?

Yes, the IA only uses the ADDR, DATA, and STAT labels.

Breaking out each signal in the STAT label into individual labels is just for convenience. It might be helpful to make some things more clear in the list display to have separate columns for the signals, and in the waveform display to have separate waveforms for the individual signals.

Also, in the trigger configuration it can be easier to specify levels or edges of individual signal labels, instead of specifying them as bits inside the STAT label. For example in the timing trigger specification screen capture in my previous reply I specified the rising edge of the -RST label as the Edge1 term, instead of specifying it in the STAT label.

[Dan Moos]

couple bits of curious behavior.

I have it set up to trigger on the first address  where my code is run. My first opcode is LDX #$FF (the usual deal for setting up the stack pointer)

The analyzer triggers as expected, shows the proper HEX for the opcode (A2), but doesn't show the mnemonic (LDX #$FF). The symbol in the STAT line says OPCODE FETCH (I just copied your settings for the STAT symbol table)

From that point on, the mnemonics are always displayed as expected. Just that one first opcode does this. Other calls to LDX immediate mode display properly, and in fact, if I trigger earlier (on the cycles where the reset and IRQ vectors are set up), when it get to that line, it works correctly.

Another curiosity, that I suspect might be a signal integrity issue again, but thought I'd throw by you.

I call PHX to save the X reg on the stack. Th analyzer output is as expected. One cycle to fetch the opcode. On cycle that is the opcode both running, and the next opcode being put on the data bus (neat to actually watch the pipelining happen!), and one cycle that is a write to the stack.

PHY is exactly the same. PHA is the same, except instead of a write to the stack, I get a read from ROM. What makes me think its a signal integrity thing, is that the low byte of the ROM address being read is the expected low byte of the stack address I wanted to write! The high byte is the high byte of the part of ROM where the program counter should be. Seems like the anaylizer is working fine, and that this must be a problem with my sketchy bread board set up. Concur?

Also, how are you getting screen shots? Does the analyzer have a way to do this, and you are grabbing them via the ethernet connection?

[gslick]

Also, how are you getting screen shots? Does the analyzer have a way to do this, and you are grabbing them via the ethernet connection?

I'll reply to the easy part first.

You can use FTP from the PC to capture a screen image. Make sure you use the FTP BIN command to set the transfer mode to binary before using GET to transfer the file from the analyzer to the PC.  (I also used an image editor on the PC to convert the TIF format image files to PNG format image files before posting them here).

The /system/graphics/screen.tif file is a dynamic file on the logic analyzer. It doesn't exist on the disk. It captures whatever is on the analyzer screen at the time the file transfer occurs.

Code: [Select]

C:\HP-1670E>ftp 192.168.1.200
Connected to 192.168.1.200.
220  HP167XE V02.02 FUSION FTP server (Version 3.3) ready.
500 Command not understood.
User (192.168.1.200:(none)): data
230 User DATA logged in.
ftp> dir
200 PORT command ok.
150 Opening data connection for  (192.168.1.103,55607).
dr-xr-xr-x    2    1    1       766  status
dr-xr-xr-x    4    1    1       894  system
dr-xr-xr-x    3    1    1       766  slot_a
226 Transfer complete.
ftp: 138 bytes received in 0.01Seconds 9.20Kbytes/sec.
ftp> cd system
200 Remote Directory changed to "/system".
ftp> dir
200 PORT command ok.
150 Opening data connection for  (192.168.1.103,55608).
dr-xr-xr-x    4    1    1       638  disk
dr-xr-xr-x    2    1    1       894  graphics
-rw-rw-rw-    1    1    1         0  program
-rw-rw-rw-    1    1    1         1  setup.raw
226 Transfer complete.
ftp: 187 bytes received in 0.03Seconds 6.03Kbytes/sec.
ftp> cd graphics
200 Remote Directory changed to "/system/graphics".
ftp> dir
200 PORT command ok.
150 Opening data connection for  (192.168.1.103,55609).
-r--r--r--    1    1    1         1  screen.pcx
-r--r--r--    1    1    1         1  screenbw.tif
-r--r--r--    1    1    1         1  screen.tif
-r--r--r--    1    1    1         1  screenbw.epi
226 Transfer complete.
ftp: 203 bytes received in 0.03Seconds 6.34Kbytes/sec.
ftp> bin
200 Type set to Image.
ftp> get screen.tif pcfilename.tif
200 PORT command ok.
150 Opening data connection for screen.tif (192.168.1.103,55611) (308934 bytes).
226 Transfer complete.
ftp: 308934 bytes received in 1.34Seconds 229.86Kbytes/sec.
ftp> bye
221 Goodbye.

[Bassman59]

right on. I think my failure has been thinking I could just attach a normal cable from the computer to the analyzer.

Any reasonably-modern computer’s Ethernet port is auto-MDX, which means that a crossover cable shouldn’t be necessary, nor should a hub or switch between the analyzer and the computer.

I have an HP1661 and I used to connect it to a PC directly all the time (two Ethernet cards in the computer). I say “used to” because I can’t remember the last time I turned it on.

[kb5mu]

I am trying to load an inverse assembler on a 1670G, but I get errors like this one:

      Insufficient memory to load IAL - load aborted

I've tried the Z80 inverse assembler (the one I want to use) and the 6502 inverse assembler (the one you're talking about in this thread).

What kind of memory is it talking about? Is there anything I can do to free some up? These should work on a 1670G, right?

Thanks for any help!

  -Paul KB5MU

[gslick]

I am trying to load an inverse assembler on a 1670G, but I get errors like this one:

      Insufficient memory to load IAL - load aborted

I've tried the Z80 inverse assembler (the one I want to use) and the 6502 inverse assembler (the one you're talking about in this thread).

What kind of memory is it talking about? Is there anything I can do to free some up? These should work on a 1670G, right?

Thanks for any help!

  -Paul KB5MU

Maybe the IA files you are trying to load are corrupted. How did you copy the IA files to the 1670G?

[kb5mu]

Thanks for helping!

I used the Python script that purports to be equivalent to IALDOWN.EXE but over Ethernet. This one:
https://bits.sigpipe.me/Software/HP/Tools/IALDOWN.py

iz80_i.r is 10616 bytes on the computer and the resulting file is 11264 bytes long on the 1670G and is recognized as type inverse_assem.

New info: the 6502 inverse assembler DOES work on my 1670G, loaded the same way. It's only 9452 bytes on the computer and 10240 bytes on the 1670G. Operator error earlier.

If I read back the two files from the analyzer via FTP, I see the same file sizes as on the analyzer, and here are MD5 hashes of them:
MD5 (i6502) = 180cb26f40a39faa8b12254f212f1bf1
MD5 (iz80_i) = 56b97d8b67cdcc668a269ec94df1d6c7

  -Paul KB5MU

[gslick]

You shouldn't need to use an IALDOWN transfer for the iz80_i.r inverse assembler.  The downloaded version of the file iz80_i is already available.  You can just do an FTP copy of the iz80_i file to the analyzer (make sure the FTP transfer mode is set to binary). The iz80_i file is what was available to customers, the iz80_i.r relocatable file version was recreated from the iz80_i file.

The iz80_i inverse assembler is set up for use with the 64683A / 10300B Z80 preprocessor. It might require a slight modification to work correctly with the analyzer connected directly to a Z80 instead of through the preprocessor. I'd have to look at some notes about that. One of the CPU status signals is inverted by the preprocessor if I remember correctly, maybe the R/W signal.

Edit: According to my notes in this thread the 10300B Z80 preprocessor does invert the /WR signal from the Z80 pin 22.
https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485

[kb5mu]

Cool, thanks! I thought I had tried the original iz80_i file, but maybe something else was wrong at the time. Now I've loaded it successfully from the distributed iz80_i file. I do wonder what went wrong with the .r file, though.

Thanks for pointing out the need for special signals to trace. I was aware of that from other postings of yours on this forum. I'm already making my own adapter PCB to plug into the Z80's system bus and hook up via HP 01650-63203 Termination Adapters, so it's easy to add the needed circuitry. At the moment I'm thinking I'll add the six inverters but skip the two buffers, but I need to think a little harder about the timing requirements before I finalize that decision. And do a breadboard test.

My prototype board is out for fab right now, but it was based on my unfounded assumption that the inverse assemblers and details on how to hook them up would be impossible to locate after all these years. I had chosen a slightly different set of signals for my equivalent of STAT, but already had to add some delays to make it work. I'm going to assume the HP engineers spent more time figuring out the best way to deal with Z80 bus timing and switch to their definition of STAT. This forum has been incredibly helpful in that regard.

Because I wasn't expecting to be able to use the analyzer's inverse assembler, I was planning to write my own post-processing program to convert a hex dump from the analyzer to a disassembly. I may still do that, because once the data is in the computer I can also combine it with actual source code, when I have it, which is far better than a primitive single-instruction disassembly.

Again, thanks!

  -Paul