IC12 (i.e. Channel 1)
Pin 8 (OUT+) = -9.73V
Pin 9 (OUT-) = -9.65V
Pin 14 (+10V) = +9.77V
Pin 3 (-10V) = -9.94V
Pin 15 (INPUT) = -1.375V
IC13 (i.e. Channel 2)
Pin 15 (INPUT) = +0.449V
Both channels controls are set identically. There is obviously something going on with the input as Ch1 is minus 1.375V and Ch2 is plus 0.449V.
The discrepancy in voltage is certainly interesting. It doesn't exonerate IC12, however, since something wrong inside IC12 could be pulling down the input pin 15.
Let's assume IC12 is ok and let's see what the dual JFET Q1 is supposed to be doing.
To start, we have the diode network of D13 + D2 and D12 + D1. D13 and D12 are both 12V zeners.
D12 cathode is connected to +10, with a pulldown to -10V via R15. That would make D12 anode -2V (approx). D13 anode is connected to -10V with a pullup to +10 via R16. D13 anode is therefore +2V. The various caps provide filtering. So, this circuit generates symmetric -2V and +2V reference points. (Hint: Those are some voltages to check.)
Q1a gate is the input to the first stage, and is connected to the reference points by diodes D1 and D2. Anything more positive than D13 anode + 0.7V (= +2.7V) will cause current to flow through D1, thereby clamping the input voltage. Conversely anything less D13 - 0.7V (= -2.7V) will be clamped through D2.
So, the input voltage to Q1a gate is limited to +/-2.7V (approx). R18 47R doesn't matter because the input current to Q1a is on the order of a few 10's of picoamps. Your reading of -1.375V is within range, but check that the -2V and +2V reference points are ok.
JFET Q1a is configured as a voltage follower. The source (the bottom) will be a couple of volts *higher* than the gate (JFETs operate reverse biased). Q1b is providing the right amount of current so that the source will be pulled back down to 0V when Q1a gate is also at 0V.
How does Q1b know how much current to provide? Well, that's why Q1a and Q1b are a matched pair. Q1b's drop from gate to source and then through R29 100R is equal to the same drop on Q1a and R28 100R.
So, that should tell you some other voltages to check. See if Q1a gate to source (Vgs) is the same as Q1b Vgs. And if you want to keep me honest, you can check Q2a and Q2b Vgs also.
I know soldering test wires to probe voltages is a pain. From your photos, it looks like you can get to Q2's leads from the top. Maybe Q1 if the potentiometer isn't too much in the way.
Here's another thought. A dynamic test on IC12's input is also possible. While watching IC13 pin 15 with your DMM, try the 9V battery DC input test on Ch2. Keep the trace on the screen. Note the two DMM readings between 0V and 9V. Then move the DMM to IC12 pin 15 and input into Ch1 and compare results. The absolute voltages may be different, but the difference between 0V and 9V input should be the same on both channels.
Perhaps do this test first before the above JFET tests since you already have those wires soldered and accessible.