Cheap and Small Dynamic Signal Analyzer?

[TopQuark]

An impulse source is even faster.  Or an edge can be used as the source and then the signal differentiated before the FFT.

With the impulse method you still need to capture enough data points to have a high resolution FFT and most importantly measure lower frequency response no? I think a periodic random noise source and the pulse method both excites all the frequency bins within the analysis span, and does the same thing. Speed is limited by the lowest frequency component you wish to analyse, correct me if I am wrong.

https://www.eevblog.com/forum/testgear/capacitive-impedance-plots-with-sds2104x-plus-bode-function/msg4338271/#msg4338271
I have previously written a simple script that turns the bode plot data from a Siglent scope into detailed LCR (mostly C) impedance analysis. I think the FPGA solution would have more than enough horsepower to do every one of those graphs in real time, and generate all those analysis every data frame. So basically a new bode plot, impedance analysis and LCR analysis every few tenth of ms (or longer, again dependent on lower limit of analysis frequency).

I think I am going to experiment with my Red Pitaya this afternoon and write some software to prototype the DSA idea.

[TopQuark]

Update.

While window shopping on mouser and refreshing my shopping cart, I suddenly saw the AD4630-24 come back in stock and immediately ordered a few. Plan now is to whip up a breakout board for the AD4630-24 with 0.1 in header connections, so I can use it with FPGA or with MCU to see what kind of platform works well enough.

If the DIY breakout board works fine, I'll cancel my order for the back ordered ADI official eval board, which has a FMC connector and so only works with high end FPGA dev boards.

I am debating if I should add a frontend and Vref to the DIY breakout board design, or keep everything modular and external so I can easily swap things out for development. I have some goodies in my inventory that should work well with the ADC chip, like LTC6655-4.096, ADA4898, AD8429, ADA4523, OPA2189 etc. 

Anyways, I am quite excited to have the AD4630-24 on order ready to ship, and will probably spend my time designing the breakout board rather than playing with the Red Pitaya.

[Berni]

https://www.testunlimited.com/pdf/an/5988-6774EN.pdf
According to page 20, a 2 channel DSA (one ch for ref, one ch for DUT output) with a noise source should make for a blazingly fast if not "real time" network analysis / bode plotting tool. I think if I want to include this function, I will indeed want to have at least 2Msps for the ADC so that the bode plot can cover lets say 100Hz to 1MHz in a single sweep.

DC2390A eval board from ADI (https://www.analog.com/media/en/technical-documentation/user-guides/DC2390AF.PDF) would be the perfect solution paired with a FPGA board, with two LTC2500-32 and two fast DAC. Shame the connector on the board is a HSMC which doesn't plug into anything I own.

I have an old Agilent 10MHz VSA boatanchor that i use as a DSA and low frequency network analyzer.

Despite the old ADC tech it has an impressively wide dynamic range and low distortion, so it can be used for measuring THD in audio and similar.

It also has the ability to show a live bode plot (updates multiple times per second). The way it does it is emitting a frequency sweep chirp out of the signal generator output that is synchronized to the capture window, then just does a FFT on the whole thing.

As for the impulse method, that also works, but is more practical when done on a square wave. Those are easier to generate correctly and suffer less dynamic range issues. One edge of the square wave is a step function, that can then be put trough a differentiator to turn it into a impulse response that can then be fed into FFT to get the frequency response. Some oscilloscopes can do this using math functions. But in general sweeps tend to make better use of the ADC than this.

[TopQuark]

https://www.testunlimited.com/pdf/an/5988-6774EN.pdf
According to page 20, a 2 channel DSA (one ch for ref, one ch for DUT output) with a noise source should make for a blazingly fast if not "real time" network analysis / bode plotting tool. I think if I want to include this function, I will indeed want to have at least 2Msps for the ADC so that the bode plot can cover lets say 100Hz to 1MHz in a single sweep.

DC2390A eval board from ADI (https://www.analog.com/media/en/technical-documentation/user-guides/DC2390AF.PDF) would be the perfect solution paired with a FPGA board, with two LTC2500-32 and two fast DAC. Shame the connector on the board is a HSMC which doesn't plug into anything I own.

I have an old Agilent 10MHz VSA boatanchor that i use as a DSA and low frequency network analyzer.

Despite the old ADC tech it has an impressively wide dynamic range and low distortion, so it can be used for measuring THD in audio and similar.

It also has the ability to show a live bode plot (updates multiple times per second). The way it does it is emitting a frequency sweep chirp out of the signal generator output that is synchronized to the capture window, then just does a FFT on the whole thing.

As for the impulse method, that also works, but is more practical when done on a square wave. Those are easier to generate correctly and suffer less dynamic range issues. One edge of the square wave is a step function, that can then be put trough a differentiator to turn it into a impulse response that can then be fed into FFT to get the frequency response. Some oscilloscopes can do this using math functions. But in general sweeps tend to make better use of the ADC than this.

Hmm... If real time bode plotting is something I wish to pursue, I wonder if it makes sense to push the sampling rate to let's say 20MSPS to get 10MHz frequency response range. The FPGA should still have enough horsepower to do real time FFT at that rate. Going from minutes to get a bode plot with the siglent scope to potentially fraction of a second per update does sound really appealing 

[David Hess]

With the impulse method you still need to capture enough data points to have a high resolution FFT and most importantly measure lower frequency response no? I think a periodic random noise source and the pulse method both excites all the frequency bins within the analysis span, and does the same thing. Speed is limited by the lowest frequency component you wish to analyse, correct me if I am wrong.

That is right.  The lowest frequency of interest determines the amount of time that the acquisition must be taken over.  The same issue comes up with low frequency noise measurements; if you want to include noise down to 0.1 Hz, then you have to make at least 10 seconds worth of measurements.

The problem with using noise as I understand it is that multiple acquisitions are necessary to account for its random nature.  From the link below:

Note that the random noise source requires that we use the averaged FFT so we can see the mean response at each frequency. This is the only way to obtain statistically significant data from the white noise source.

Despite the old ADC tech it has an impressively wide dynamic range and low distortion, so it can be used for measuring THD in audio and similar.

It also has the ability to show a live bode plot (updates multiple times per second). The way it does it is emitting a frequency sweep chirp out of the signal generator output that is synchronized to the capture window, then just does a FFT on the whole thing.

As for the impulse method, that also works, but is more practical when done on a square wave. Those are easier to generate correctly and suffer less dynamic range issues. One edge of the square wave is a step function, that can then be put trough a differentiator to turn it into a impulse response that can then be fed into FFT to get the frequency response. Some oscilloscopes can do this using math functions. But in general sweeps tend to make better use of the ADC than this.

Here is an old EDN article which discusses the three methods.  The swept sine method naturally has the highest dynamic range.

[TopQuark]

https://www.eevblog.com/forum/testgear/siglent-sds2000x-hd-12bit-(published-for-chinese-domestic-market-only)/msg4489057/#msg4489057
Gave the DSA bode plot method a shot with my 12-bit scope, wrote a bit of software to try out the method. In my experiments noise seems to work best, as my function gen can't produce burst sweep chirp with 0v on either end, it is either continuous sweep or burst at fixed frequency. 

I currently have 3 directions I can pursue for the DSA project.

1. Go for the AD4630-2. Two channel 2 Msps @ 24 bits will make for a really high dynamic range DSA under 1MHz. Need to design my own breakout board, but chips is on the way. Sampling rate is low enough that a MCU might be good enough, might not need FPGA.

2. Go for ADC3683EVM. Two channel 65 Msps @ 18 bits. Good dynamic range, can look at signal under 30MHz and oversample for lower frequencies. Plug and play FMC card. Firmly in FPGA territory. I have a board on the way, might use it for the DSA project, or use it elsewhere.

3. Red pitaya. 125 Msps @ 14 bits. Can swap the ADC chip to LTC2185 for 16 bits and improve SNR by 3-4dB. I already have the board, everything is wired up well, DAC included. FPGA on board.

For my DSA needs, I only need to look at signal under 1MHz. But if I am to spend the trouble and effort to develop the project, I would want to have it work as a bode plot machine as well, and so I would want to have it work up to 10MHz. So currently I am leaning towards options 2 and 3.

[TopQuark]

Look what arrived in the mail today 

The ZU15EG FPGA SoC probably has more horsepower than most entry level scopes, and the ADC3683 is one hell of an ADC. Not cheap, nor small, but at least the hardware has the potential of being a kickass DSA.

[KE5FX]

Cool ADC, but wow, what a brain-damaged clocking architecture.  If I'm reading the data sheet right, the LVDS output is synchronous to the sampling clock, but you have to supply the clock.  Oh, yes, and it has to run at rates like 4.5x SCLK in some of the more useful modes.   

If they hadn't bungled the digital side so badly, that chip wouldn't even need an FPGA.

[TopQuark]

Yea it is pretty silly. Current thinking is to clock the ADC sampling clock input with a low jitter source. Data frame clock output (same freq as sampling clock, with delay and likely more jitter) from the ADC will be used to sync the data frame transfer and create the bit timing clock with a PLL on the FPGA.