You are right, and this should not be neglected: An implicit analog BW limit of 70 to 350 MHz is always present in the AFE, depending on the model.
Edit: Possibly one should really measure the noise floor SPD at different settings, like Performa01 did for the Siglent.
As I pointed out earlier, any bandwidth limit, including high resolution mode, lowers the spot noise (1) but does nothing for the noise density. For lower noise density, better or more suitable devices are required.
(1) Above the flicker noise corner frequency, RMS Spot noise = Noise Density * Sqrt(Noise Bandwidth)
Skipping samples to reduce the data rate instead of averaging (or a similar filter with slightly different weights) adjacent samples will cause some aliasing and this way also the measured noise density.
Another way to say that is aliasing folds the noise bandwidth over below the Nyquist frequency increasing the noise density so that the spot noise remains the same. This does not apply to ADCs in DSOs from Tektronix and Keysight and other high end manufacturers which perform noise shaping, but that does nothing for the noise from earlier stages.
It depends of the noise of the input stage on how important the later stage and ADC noise is.
In case of the Rigol sope it looks like most of the noise comes from the input stage, even though the ADC part is way higher BW than actually needed.
In an integrated CMOS design, it would not surprise me if the noise of the preamplifier following the input buffer is as high or higher in some cases. Companies like Tektronix and Keysight can rely on exotic processes to achieve much better noise performance for a given bandwidth than available with CMOS. Otherwise JFETs provide the lowest noise but are limited to lower bandwidth.
I wonder what the fastest available JFET is these days. My Tektronix notes list the 2N5397 at 260 MHz but that was as of 1982, and faster JFET front ends even in 1984 used hybrid construction.
On the other hand, a Toshiba 3SK293 dual gate MOSFET comes out to 1.5 GHz so if someone wants to home build a faster front end, or an active probe, the parts are available.
Especially for the lower BW versions a more conventional input stage would be a much better choice and not necessary that expensive.
I hope they considered it and decided that their intended market did not require lower noise so it would have been an unnecessary expense. Otherwise it is just bad design.
The best solution with the existing Rigol ASIC would be a separate input buffer with lower bandwidth and lower noise followed by a preamplifier with enough gain to overcome the noise of the following stages, but doing this would make the lower bandwidth models cost more to produce than the higher bandwidth models? Rigol is making these things incredibly cheap.