I thought why not to replace electrolytic capacitors as they seem to me to be low quality.
To start with PSU: there are:
1. 100 uF x 400 V (150C)
2. 47 uF x 35 V
3. 22 uF x 16 V
4. 1000 uF x 16 V (4 pc)
5. 47 uF x 25 V
6. 1000 uF x 25 V
7. 100 uF x 35 V
I would like to know is there is a way to improve PSU by increasing capacitance or voltages of this caps? Should I use low impedance/ESR caps?
Besides, there are 6 1000 uF x 10 V and 8 220 uF x 16 V and one 470 uF x 25 on mainboard, any suggestions what to with them?
to replace caps without exact knowldge of PSU details it will not improve anything.
Let me tell you about the power supply on these DSOs (this is for the
old hardware revisions only)
The PSU is delivering some voltages, especially +5 and +3.3V are important.
Channels and Trigger Input circuit is using own LDO, the ripple is low enough to say that these are good designed.
Still, these LDOs can be replaced by better once, mit higher PSSR and lower noise. These LDOs are located on
the left side of the main PCB.
FPGA is using two additonal LDOs, they good enough (ok, AMS1117 is not the best one, but should have no influence on DSO quality)
SoC is using two additional LDOs too, same as fr FPGA - they can be replaced by better LDOs but not really important.
ADCs and part of trigger circuit is using 3.3V coming directly from the PSU, the ripple is =< 20mV. This is not the best design at all,
especially for ADC/DAC there should be something better in place.
The 3.3V on the PSU will be created from the 5V, decreased a bit by Schottky diode and followed by Fairchild KA378R33.
The Schottky diode is reducing the LDO input voltage to reduce LDOs Power Dissapation, which make sense because the heatsink
is two numbers to small anyway. The Fiarchild KA378R33 is not designed the best choice, the PSSR is low, noice level high and it is
to slow responding. A ugly chinese/cost-reduction design.
A good replacement (note, the 3.3V will be used for other voltages creation too, like FPGA, SoC, and used by all logic ICs - this is
giving some load and need fast response LDOs) could be something like LT1585, of course the ugly Schottky diode need to be removed too
as the LT1585 have a bit higher droupout voltage.
For ADCs and part of the DAC/trigger circuit where this voltage will be used a separate solution is the only way,
there are no LDOs with such low dropout volage (well, there are some , but initial min. voltage is higher than these 3.3V)
As the 3.3V will be anyway generated from the 5V, we can take the 5V and generate proper 3.0V for ADCs,DAC and trigger IC separatelly.
Luckily each part of affected circuit can be easily disonnected from the 3.3V - by removing of the ind. filters on the main pcb.
Top side ADCs are then separated from bottom side ADCs and from DAC/Trigger. Each these groups is using not more
than 90mA (two or single chan, 1GSs, highest resolution, highest memory tested, with high loaded input and ext. trigger)
so with 3 low noise/high PSSR LDOs a really clean and stable voltage can be generated - for example with LP5900SD-3.0
If you look on the Instek DSOs (which is the original design for input/ADCs circuit used later by Hantek/Tekway/Rigol), you will see that
the power supply is generated in proper way, every ADC have all recommended decoupling caps, ADCs having own LDOs and so on.
Then Rigol - they removed some decoupling caps and started with the crap voltage thing (one 3.3V, a cheap low ESR caps),
and then Hantek/Tekway - they removed again some (well, only one per ADC) decoupling caps ... is it really bad ? Well sure,
far away from what AD is recomending for the AD9288, is it working ? Sure, but not the best design.
Why this happens ? Well, as EE you can design nice things, but then you have still to sell them, so it was probably cost reducion thing
afterall. For an EE no a big deal to create proper voltages (or solder 8 decoupling caps like i did), but i don't like it.
To be very honest i recognized this "issues" first as i was testing better (from overclocking and SNR point of view) ADCs (AD9218), they need better power supply and as i started
to trace i found out "ups, someone was too smart and removed too much parts".
Probably Hantek will answer "no our EE tested everything and 20mV ripple is not too much for ADCs"
![Tongue :P](https://www.eevblog.com/forum/Smileys/default/tongue.gif)
Anyway, even with additional decoupling caps or better 3.3V voltage, i don't think it will have a real big influence
on the skew time issue, or warm-up drift or noise level by 1GSs (but maybe i'm wrong).
I have here tons of high quality LDOs/parts, in a free "minute" i will test it a bit and report back. So for now, don't replace caps as they
not a real issue.