Internal voltages that cross the isolation are 5, 1.8, and 3.3. On the footprint marked P11, the voltages are +3V3, GND, +1V8, GND, +5, GND.
FPGA JTAG pinout is not Xilinx standard. From the marked end of the connector, pinout is +3V3, TCK, TDI, TDO, TMS, GND. I got it to show up in Impact correctly as an xc6slx16.