When set to HDG6162B, the output of the HDG2000 is divided by 2. A 160Mhz Sine set on the HDG shows at 80Mhz on the scope. This would be compatible with a DAC 2xfaster and the HDG firmware adapting the FPGA output to the DAC to reach the "supposed" correct sampling rate of the AD9783... am I wrong?
yes, that make sense.
This also would mean that the current firmware knows more than only the HDG6xxxx max input frequencies.
What do you think?
the firmware have multiple binaries, hard to follow what/where is responsible for what. But assuming they too lazy,
the firmware (ARM part of it) will be able to control HDG6000 as well. The question is, where these 160MHz has been defined.
If in ARM firmware (and DDS firmware in FPGA is talking whatever ARM is sending), then one have to find it and patch, to e.g. 200MHz. Here is of course extra aspect - dds output is not everything, how is then the rest of hardware at 200MHz?
It can be as well that the FPGA firmware for HDG6xxx is different. But maybe there is way to check it. When you have
changed your AWG to HDG6xxx, and set 160MHz clock (probably it will be work in lower clocks as well, but let try the limit to ensure that no other option, from lower models, has been trigered), then you can measure the DAC clock. If the FPGA design is universal, you will see here 500MHz. This will be probably too much for the DAC and it will cloock on every second edge, so 250MHz.
But when you see 250MHz on DAC clockin, then the FPGA design is not universal and it is simply trying to set something based on control code from ARM fw.