Hantek HDG2002B AWG: 5Mhz or 100MHz? Let's see!

[fremen67]

And for those having a x64 system, here are the drivers for the HDG uboot

[tinhead]

There is something strange I forgot to mention regarding the power supply.

As you see on the first page pictures, there are two power supply connectors on the board, one on each extremity.

Would it mean that Hantek run into design problems and did that as a workaround? What do you think?

when you look exactly the PSU PCB, then you will see that there are two complettly separate transformers. One seems to generate all power rails for analog part, the other (small) one for digital part and fan. So it looks like when the opto isolation option has been populated (you remember, there is currently small PCB soldered instead of opto-isolation module) the 4pin connector need to be then connected to that 4pin right conector to supply digital part of the PCB.

[fremen67]

So it looks like when the opto isolation option has been populated (you remember, there is currently small PCB soldered instead of opto-isolation module) the 4pin connector need to be then connected to that 4pin right conector to supply digital part of the PCB.

That makes sens. I suppose it is meant for the HDG2000C Series. Could it also be a way to have a cleaner signal on the output?

[leppie]

So it looks like when the opto isolation option has been populated (you remember, there is currently small PCB soldered instead of opto-isolation module) the 4pin connector need to be then connected to that 4pin right conector to supply digital part of the PCB.

That makes sens. I suppose it is meant for the HDG2000C Series. Could it also be a way to have a cleaner signal on the output?

Actually, it seems to be for the 6000 series. You can see it on the Chinese site. http://www.hantek.com/ProductDetail_8_152.html In the specs tab, it notes isolation. It does come with a faster DSS chip though (500MS/s). Overclocked maybe?

[tinhead]

Actually, it seems to be for the 6000 series. You can see it on the Chinese site ... In the specs tab, it notes isolation.
It does come with a faster DSS chip though (500MS/s). Overclocked maybe?

AD9783 is pin-compatible 2ch 500MS/s 16bit DAC. Sure it need LVDS instead of LVCMOS interface,
but that not a big deal when using FPGA to provide the data. So to get HDG6xxx one need new DAC,
some passives, isolation PCB (what so ever they used for), OCXO and firmware dump from such AWG.
The PCB label shows HDG2000 and not HDGx000, but that might be coming from late decision etc.
So yeah, HDG6000 might really be using same PCB/PSU.

[fremen67]

Actually, it seems to be for the 6000 series. You can see it on the Chinese site ... In the specs tab, it notes isolation.
It does come with a faster DSS chip though (500MS/s). Overclocked maybe?

AD9783 is pin-compatible 2ch 500MS/s 16bit DAC. Sure it need LVDS instead of LVCMOS interface,
but that not a big deal when using FPGA to provide the data. So to get HDG6xxx one need new DAC,
some passives, isolation PCB (what so ever they used for), OCXO and firmware dump from such AWG.
The PCB label shows HDG2000 and not HDGx000, but that might be coming from late decision etc.
So yeah, HDG6000 might really be using same PCB/PSU.

At least the firmware won't be too different from the one in our HDG as it already knows the HDG6162B. If you use this name, the sinus waveform is unlocked up to 160Mhz  , exactly what is described on the Hantek site...
As the FPGA is configured through a file (/lib/firmware/htg1000.bit) we could imagine that this file could be enough for the software mod ... or at least not far.

[fremen67]

Another thing regarding the potential HDG6xxxx mod.
When set to HDG6162B, the output of the HDG2000 is divided by 2. A 160Mhz Sine set on the HDG shows at 80Mhz on the scope. This would be compatible with a DAC 2xfaster and the HDG firmware adapting the FPGA output to the DAC to reach the "supposed" correct sampling rate of the AD9783...  am I wrong?
This also would mean that the current firmware knows more than only the HDG6xxxx max input frequencies.
What do you think?

[FrankenPC]

Playing with the signal generator finally...I got my Rigol back from repair.  So, I don't see any impedance compensation option.  There is none right?

Anyway to check for firmware updates?  Is there a Hantek firmware site?  This thing locks up in really weird ways.

[fremen67]

Playing with the signal generator finally...I got my Rigol back from repair.  So, I don't see any impedance compensation option.  There is none right?

Didn't see any option. It seems to be 50 ohms.

Anyway to check for firmware updates?  Is there a Hantek firmware site?  This thing locks up in really weird ways.

This the link: http://www.hantek.com/en/ProductDetail_149.html but no update at the moment, and yes it would definitely need one.

All of you having a HDG, could you post your software and hardware version? I think it will be faster to update with a backup of one of us when it is a new one. Mine are:
Software 1.00.1 (140402.0)
FPGA 11
PCB 1002

[tinhead]

When set to HDG6162B, the output of the HDG2000 is divided by 2. A 160Mhz Sine set on the HDG shows at 80Mhz on the scope. This would be compatible with a DAC 2xfaster and the HDG firmware adapting the FPGA output to the DAC to reach the "supposed" correct sampling rate of the AD9783...  am I wrong?

yes, that make sense.

This also would mean that the current firmware knows more than only the HDG6xxxx max input frequencies.
What do you think?

the firmware have multiple binaries, hard to follow what/where is responsible for what. But assuming they too lazy,
the firmware (ARM part of it) will be able to control HDG6000 as well. The question is, where these 160MHz has been defined.
If in ARM firmware (and DDS firmware in FPGA is talking whatever ARM is sending), then one have to find it and patch, to e.g. 200MHz. Here is of course extra aspect - dds output is not everything, how is then the rest of hardware at 200MHz?
It can be as well that the FPGA firmware for HDG6xxx is different. But maybe there is way to check it. When you have
changed your AWG to HDG6xxx, and set 160MHz clock (probably it will be work in lower clocks as well, but let try the limit to ensure that no other option, from lower models, has been trigered), then you can measure the DAC clock. If the FPGA design is universal, you will see here 500MHz. This will be probably too much for the DAC and it will cloock on every second edge, so 250MHz.
But when you see 250MHz on DAC clockin, then the FPGA design is not universal and it is simply trying to set something based on control code from ARM fw.

[FrankenPC]

Software 1.00.1 (140402.0)
FPGA 12
PCB 1002

[tinhead]

FPGA 12

if you don't mind please make copy of what inside /lib/firmware/ directory, zip and post it here

[FrankenPC]

FPGA 12

if you don't mind please make copy of what inside /lib/firmware/ directory, zip and post it here

Sure...I'm not that familiar with Linux.  Do I mount a USB drive?  How do I go about that?

[fremen67]

Sure...I'm not that familiar with Linux.  Do I mount a USB drive?  How do I go about that?

Yes, insert a USB drive in the HDG. It will be automatically detected and mounted in /mnt/udisk (you will see a USB sign on the upper left corner of the HDG screen and it will also beep). Connect to the the HDG the way you did for the software hack and type the following command:

tar -cvf /mnt/udisk/hdg_lib /lib/firmware

It will create a file on your USB drive (hdg_lib). After that you can remove the USB drive, plug it on your PC, zip the file and post it here. 

[FrankenPC]

Sure...I'm not that familiar with Linux.  Do I mount a USB drive?  How do I go about that?

Yes, insert a USB drive in the HDG. It will be automatically detected and mounted in /mnt/udisk (you will see a USB sign on the upper left corner of the HDG screen and it will also beep). Connect to the the HDG the way you did for the software hack and type the following command:

tar -cvf /mnt/udisk/hdg_lib /lib/firmware

It will create a file on your USB drive (hdg_lib). After that you can remove the USB drive, plug it on your PC, zip the file and post it here. 

Thanks!

[fremen67]

- check first if the clock is really generated by FPGA (from pictures it looks like it is), if not, think wtf wrong here?

Yes it is. Pins 3&4 of the DAC are comming from C191&C187 just near the FPGA. If you prevent the fpga from being configured (ie moving htg1000.bit) than there is no signal anymore on c191&c187.

What I would do is to:
- check first if the clock is really generated by FPGA (from pictures it looks like it is), if not, think wtf wrong here?
- measure (and at least check) how the DAC clock looks like
- is it variable?

250Mhz sine all the time. A variable frequency would have an impact on both output channels. Wouldn't it?

[fremen67]

It can be as well that the FPGA firmware for HDG6xxx is different. But maybe there is way to check it. When you have
changed your AWG to HDG6xxx, and set 160MHz clock (probably it will be work in lower clocks as well, but let try the limit to ensure that no other option, from lower models, has been trigered), then you can measure the DAC clock. If the FPGA design is universal, you will see here 500MHz. This will be probably too much for the DAC and it will cloock on every second edge, so 250MHz.
But when you see 250MHz on DAC clockin, then the FPGA design is not universal and it is simply trying to set something based on control code from ARM fw.

When set to HDG6162B, the DAC clockin is still 250Mhz and the frequency output is divided by 2 for all the frequencies.
So the ARM part seems OK but the FPGA not. We would have to find the correct htg1000.bin or patch it.
I also saw jitter in the DAC clockin but I don't trust my MSO.
Something wired: Channel 1 is output 2 of the DAC and vice-versa 

The limits when configured as HDG6162B are:
160Mhz sine
50Mhz square
4Mhz ramp
500khz pulse
This does not seem correct...

[FrankenPC]

FPGA 12

if you don't mind please make copy of what inside /lib/firmware/ directory, zip and post it here

See attached tar file.

[fremen67]

See attached tar file.

Thank you. Your FPGA firmware (v12) was build on April 18th and mine (v11) on April 2nd.
Good thing that they are working on it so quickly (well, at least from bug correction point of view, not from stability point of view )
May be others with a newer HDG will have newer versions...
I did not see the difference at the moment.

The "ghost" waveforms that one can see on square waves are still there. I suspect a firmware bug rather than a hardware one as you dont see them when using the pulse function at the same rate. The pulse function also has a bug as it only create waves with frequencies that are sample rate divided(f.e. 19.230769Mhz wich is SR/13).
Compare a square wave @19.230769Mhz and a pulse wave at the same frequency: square has ghosts, pulse not.

[idpromnut]

Same version info for me:

Software 1.00.1 (140402.0)
FPGA 12
PCB 1002

[Control:Eng]

Just wanted to let you know that I got an english Manual from my seller today.

He say's that it's the officiale one that Hantek gave him the day before.

I didn't compare it to the google-translated one...but this one also has the pictures in it.

See attachment

The original .docx file is to large to upload it here. That's why I uploaded it as .pdf

I just also asked him whether Hantek plans to release a new Firmware version in the next weeks since of the stability issues.

[FrankenPC]

Just wanted to let you know that I got an english Manual from my seller today.

He say's that it's the officiale one that Hantek gave him the day before.

I didn't compare it to the google-translated one...but this one also has the pictures in it.

See attachment

The original .docx file is to large to upload it here. That's why I uploaded it as .pdf

I just also asked him whether Hantek plans to release a new Firmware version in the next weeks since of the stability issues.

I wonder is some new and interesting feedback mechanism is happening here. 
A company releases a product. 
A hacking community is attracted to that product. 
They hack the product.
More people buy the product as a result of that hack.
The product is modified and upgraded as a result of the new found interest (profit)

In other words: Hacking actually makes the product better.  Trickle down hacking

[IanJ]

1.00.2(140422.0) here as purchased.

I am able to use LAST settings i.e. on reboot where it remembers my previously entered parameters and turn off the screensaver etc

I notice that if I select LAST under system status/startup.............then on reboot I get the chinese UI (oh sh!t), not the black screen others are getting. But if I then hit UTILITY, select the 1st icon and then hit F1 I can select English menu back.......phew!.

But from then on it's English, and loads LAST settings etc.

Ian.

[fremen67]

1.00.2(140422.0) here as purchased.

Thank you Ian for the information. What version of FPGA do you have?

[IanJ]

1.00.2(140422.0) here as purchased.

Thank you Ian for the information. What version of FPGA do you have?

Software = 1.00.2(140422.0)
Kernel = 3.2.35
FPGA = 12
Keyb = 1

Ian.