There is something strange I forgot to mention regarding the power supply.
As you see on the first page pictures, there are two power supply connectors on the board, one on each extremity.
Would it mean that Hantek run into design problems and did that as a workaround? What do you think?
So it looks like when the opto isolation option has been populated (you remember, there is currently small PCB soldered instead of opto-isolation module) the 4pin connector need to be then connected to that 4pin right conector to supply digital part of the PCB.
So it looks like when the opto isolation option has been populated (you remember, there is currently small PCB soldered instead of opto-isolation module) the 4pin connector need to be then connected to that 4pin right conector to supply digital part of the PCB.That makes sens. I suppose it is meant for the HDG2000C Series. Could it also be a way to have a cleaner signal on the output?
Actually, it seems to be for the 6000 series. You can see it on the Chinese site ... In the specs tab, it notes isolation.
It does come with a faster DSS chip though (500MS/s). Overclocked maybe?
Actually, it seems to be for the 6000 series. You can see it on the Chinese site ... In the specs tab, it notes isolation.
It does come with a faster DSS chip though (500MS/s). Overclocked maybe?
AD9783 is pin-compatible 2ch 500MS/s 16bit DAC. Sure it need LVDS instead of LVCMOS interface,
but that not a big deal when using FPGA to provide the data. So to get HDG6xxx one need new DAC,
some passives, isolation PCB (what so ever they used for), OCXO and firmware dump from such AWG.
The PCB label shows HDG2000 and not HDGx000, but that might be coming from late decision etc.
So yeah, HDG6000 might really be using same PCB/PSU.
Playing with the signal generator finally...I got my Rigol back from repair. So, I don't see any impedance compensation option. There is none right?
Anyway to check for firmware updates? Is there a Hantek firmware site? This thing locks up in really weird ways.
When set to HDG6162B, the output of the HDG2000 is divided by 2. A 160Mhz Sine set on the HDG shows at 80Mhz on the scope. This would be compatible with a DAC 2xfaster and the HDG firmware adapting the FPGA output to the DAC to reach the "supposed" correct sampling rate of the AD9783... am I wrong?
This also would mean that the current firmware knows more than only the HDG6xxxx max input frequencies.
What do you think?
FPGA 12
FPGA 12
if you don't mind please make copy of what inside /lib/firmware/ directory, zip and post it here
Sure...I'm not that familiar with Linux. Do I mount a USB drive? How do I go about that?
Sure...I'm not that familiar with Linux. Do I mount a USB drive? How do I go about that?Yes, insert a USB drive in the HDG. It will be automatically detected and mounted in /mnt/udisk (you will see a USB sign on the upper left corner of the HDG screen and it will also beep). Connect to the the HDG the way you did for the software hack and type the following command:
tar -cvf /mnt/udisk/hdg_lib /lib/firmware
It will create a file on your USB drive (hdg_lib). After that you can remove the USB drive, plug it on your PC, zip the file and post it here.
- check first if the clock is really generated by FPGA (from pictures it looks like it is), if not, think wtf wrong here?
What I would do is to:
- check first if the clock is really generated by FPGA (from pictures it looks like it is), if not, think wtf wrong here?
- measure (and at least check) how the DAC clock looks like
- is it variable?
It can be as well that the FPGA firmware for HDG6xxx is different. But maybe there is way to check it. When you have
changed your AWG to HDG6xxx, and set 160MHz clock (probably it will be work in lower clocks as well, but let try the limit to ensure that no other option, from lower models, has been trigered), then you can measure the DAC clock. If the FPGA design is universal, you will see here 500MHz. This will be probably too much for the DAC and it will cloock on every second edge, so 250MHz.
But when you see 250MHz on DAC clockin, then the FPGA design is not universal and it is simply trying to set something based on control code from ARM fw.
FPGA 12
if you don't mind please make copy of what inside /lib/firmware/ directory, zip and post it here
See attached tar file.
Just wanted to let you know that I got an english Manual from my seller today.
He say's that it's the officiale one that Hantek gave him the day before.
I didn't compare it to the google-translated one...but this one also has the pictures in it.
See attachment
The original .docx file is to large to upload it here. That's why I uploaded it as .pdf
I just also asked him whether Hantek plans to release a new Firmware version in the next weeks since of the stability issues.
1.00.2(140422.0) here as purchased.
1.00.2(140422.0) here as purchased.Thank you Ian for the information. What version of FPGA do you have?