There is some slight oddity with bandwidth vs. range. I was expecting bandwidth to drop as voltage in gets higher, but, its not that straightforward. These are the stock hardware results:
Range Bandwidth (MHz)
1V 605
500mV 610
200mV 620
100mV 630
50mV 580
20mV 590
10mV 590
So if you are testing standardize on what range you are going to use. 100mV gave the greatest bandwidth for me.
I played with 12nH, 15nH, 0R swap in place of 47nH. The 15nH does give a boost in frequency range but not nearly what you would expect. From -3dB of 630MHz to maybe 670MHz or so. As demonstrated above, you do see the ADC noise extend out further:
Notes:
- There was no difference in bandwidth with 12nH over 15nH, so the limitation does not lie there.
- Using 0R resistors across the inductors gave me no significant improvement over stock (odd).
- Removing the 1pF at the front of the CLC made things either slightly worse or did nothing.
- Adding a MSO7000 style RCL filter at the front end did improve bandwidth up to ~700MHz but at the cost of ~3dB of peaking at 400MHz. Too much IMO.
The 400MHz peak might be due to poor choice of components (4.7nH, 17pF, 22R), or due to another filter further down the chain.
The signal generator used was rated 6GHz, 15dBm +/-1.5dBm.
I don't have a FET probe to look at the signal along the way, that might be useful. Also could be some external passives on the AFE used to set something.