So lets get back on track
We've been digging around the scope and the software, and found that next to the Zynq (Artix-7) FGPA, Spartan-6 FPGA and ASIC FPGA (for the keyboard) there seems to be 2 more programmable devices, a CPLD and a Kintex 7.
The Spartan 6 has an eeprom with a very basic and simple bin (stripped bit more or less) in it. My edudcated guess is that the spartan stems from the DS1000Z design and 'controls' the frontend (Voltage Scale, timebase etc etc) through simple commands. The eeprom serves two purposes, to store the bitstream and to store the settings, so that when you boot up the scope, it can go into the mode it was in before. Sadly I do not have the scope myself (yet, it's sold out everywhere for the 4chan unit) so haven't confirmed this. There seems to go a bus between the eeprom .
The Spartan-6 has about 4 wires going to the Zynq (spi-ish bus?) 4 tot he eeprom on different pins and some 4 wire bus to the TOP BIG heatsinked chips.
Further more we found that the Zynq has a big wide 8 bits differential bus between the TOP BIG heatsinked chip and it self. So that's probably their main high-speed data path.
Now, the software seems to have 4 tools related to these parts. spi2*. where spi2k7 is the 'upload' tool for 2 fpga's it seems. Looking at that tool there seems to be a new spidev IOCTL which appears to switch between 'chip 0 and chip 1'. whatever that may be. The bitstream gets uploaded to chip1, but chip 0 serves as sort of arbitrarer. spi2cpld seems to interact only with chip 0. Not sure yet what this tool can do other then poke and change registers.
So rigol seems to have added a chipselect through a new IOCTl because ... of reasons. My educated guess is, they did not have enough general purpose GPIO pins, and used some of the zynq pins. Rather then to convert those to general purpose IO pins and connect them to linux, they manually hacked around a bit in the spidev driver. Very sad, but that's how it seems to be. More on that later I guess
Anyway, all pictures do not show any of this information due to the big heatsinks.
We do know that we have 4 rigol front end 'controllers' but those are fully analog chips. Those 4 differential analog traces go into the LOWER BIG chip, which we all expect to be the adc. From the ADC, we see balanced traces going to the TOP chip. Those are probably digital signals.
The going theory for now is, that their 'aquisition' chip does not exist (yet) and actually is a Kintex-7 FGPA, which takes those ADC signals, and puts them on a high-speed 8 bits datapath to the zynq. But where is this CPLD then? Is the spartan the CPLD and have they named it as such as it has a dedicated eeprom and should be treated as such? Or do we have more chips under those heatsinks.
So to anyone listening, especially who have a broken scope already (or are experts at removing and re-adding those big phat heatsinks); anybody out there that can remove those heatsinks (under their own accord, nobody here will be responsible of course) and take some high-res foto's of what's underneat?