I've heard that Rigol adds High-Resolution to Acquire Mode for new firmware version. If this feature is available on your scope, Then congratulations!
I would like to post an SPI Flash dump on this thread and some other hack on appEntry. BTW, we have a u-boot dump without tear it down (In fact, the u-boot itself contains a command to switch between NOR and NAND Flash, because they share several pins), analyzing it is little troublesome. Althrough we know the u-boot passphrase, but how to check in u-boot it still remains a mystery.
Not sure why this information would get you banned. U-Boot is GPL software for one. Secondly the software is already being shared via the forum.
Now, what are you talking about with NAND flash and NOR flash being shared via the same pins? So lets first assume this is possible, now, u-boot SPL (or the FSBL; calling it only FSBL for now) is being read via the bootrom. The bootrom uses the BOOT_MODE pins to configure the BootROM to boot from qspi SPI NOR flash. It happily reads the FSBL into the OCM (or via XIP even) and starts to execute the FSBL. U-boot is then loaded, but has no knowledge of the QSPI flash and only has the NAND pinmux set and loads the files from NAND.
What is special here, and I'm sure they can hack this into their u-boot, is that the SPL does have QSPI support, but u-boot regular does not. Because of that, I think they are using the vivado FSBL, as doing this with plain u-boot requires some hacks, as it does not support this.
Now, looking at Table 2-4, MIO-at-a-Glance; page 52 of the Zynq-7000 TRM (UG585) we see that the QSPI pins are part of pins 2 through 13, and the nand flash is 24 through 40. So there is no overlap. Now you also speak of SRAM and NOR. Yes, the zynq can boot via NOR flash, like nand, but not SPI, parallel NOR flash. Also confusingly the zynq supports SRAM, now I know the difference between the two, but some of the texts I found make it sound like there is also NOR based SRAM, which confuses me. So I think, for now, that it's either/or.Reason I bring this up is because there are 2 SRAM chips connected to the zynq (top 2 chips via snake-trace). So it could be that these are connected to the PS via these pins 40 - 53 or they are part of the FPGA. Can't see that yet ... and don't know what the purpose would be of this yet. I don't see any linux configuration for it (but I may have glanced over it). I strongly believe it is part of the FPGA and is used as some sort of buffering mechanism for the big data stream.
As for the extracted data, please do feel free to send it to me in a PM
Edit: I was wrong. The NAND pins are indeed shared. I was looking at, what turns to be out, just the text field which was put RIGHT of the pins. Super annoying.
This does make things more interesting.
So, while we cannot touch u-boot, but it's quite likely, that neither can rigol. As they cannot access it from linux nor u-boot due to the pin-sharing with nand.
Well partially true; if you disable NAND, you can freely access SPI Flash again. As linux is running from nand, re-muxing it runtime; impossible
So in u-boot; there is sf probe, which could free the nand mux and force the spi mux, but that requires patches to u-boot, which are probably complex.
That said, loading a u-boot that does have SPI Flash support (and disables nand) is also possible. I don't know if we can do a switcheroo however
So my guess, is they intended the SPI flash to be written at the factory once, and never be updated.